1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/modules/bluespec/Pygar/lab4/BranchPred.bsv	Fri Apr 23 02:32:05 2010 -0400
     1.3 @@ -0,0 +1,41 @@
     1.4 +import RegFile::*;
     1.5 +import ProcTypes::*;
     1.6 +import FIFO::*;
     1.7 +
     1.8 +typedef Maybe#(Addr) BrPred;
     1.9 +typedef Bit#(4) BPindx;
    1.10 +
    1.11 +typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq);
    1.12 +
    1.13 +typedef union tagged
    1.14 +{
    1.15 +  BrPair Valid;
    1.16 +  void Invalid;
    1.17 +} CBranchPath deriving(Bits, Eq);	// have the cache start out invalid and add valid values.
    1.18 +
    1.19 +interface BranchPred;
    1.20 +   method BrPred get(Addr pres);  //returns a maybe type that is invalid if no predition
    1.21 +   method Action upd(Addr pres, Addr next);
    1.22 +endinterface
    1.23 +
    1.24 +module mkBranchPred(BranchPred);
    1.25 +
    1.26 +   //state variables
    1.27 +   RegFile#(BPindx, CBranchPath)  bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx)
    1.28 +
    1.29 +   method Action upd(Addr pres, Addr next);
    1.30 +      BrPair brp;
    1.31 +      brp = BrPair {brpc:pres, nextpc:next};
    1.32 +      bcache.upd(pres[5:2], tagged Valid brp);
    1.33 +   endmethod
    1.34 +
    1.35 +   method BrPred get(Addr prespc);
    1.36 +      BPindx rd = prespc[5:2];
    1.37 +      let cbp = bcache.sub(rd);
    1.38 +      if (cbp matches tagged Valid .bp &&& bp.brpc == prespc)  //make sure that the read value was actually put there and the full address matches
    1.39 +	 return tagged Valid bp.nextpc;
    1.40 +      else return Invalid;
    1.41 +   endmethod
    1.42 +   
    1.43 +endmodule
    1.44 +