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comparison modules/bluespec/Pygar/lab4/Core.bsv @ 8:74716e9a81cc pygar svn.9

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[svn r9] Pygar now has the proper directory structure to play nicely with awb. Also, the apm file for audio-core willcompile successfully.
author rlm
date Fri, 23 Apr 2010 02:32:05 -0400
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7:7393cd19371e 8:74716e9a81cc
1 // The MIT License
2
3 // Copyright (c) 2009 Massachusetts Institute of Technology
4
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
11
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
14
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
22
23 import Connectable::*;
24 import GetPut::*;
25 import ClientServer::*;
26
27 //AWB includes
28 `include "asim/provides/low_level_platform_interface.bsh"
29 `include "asim/provides/soft_connections.bsh"
30 `include "asim/provides/common_services.bsh"
31
32 // Local includes
33 `include "asim/provides/processor_library.bsh"
34 `include "asim/provides/mem_arb.bsh"
35 `include "asim/provides/instruction_cache.bsh"
36 `include "asim/provides/data_cache.bsh"
37 `include "asim/provides/processor.bsh"
38
39
40
41 interface Core;
42
43 // Interface from core to main memory
44 interface Client#(MainMemReq,MainMemResp) mmem_client;
45
46 endinterface
47
48 module [CONNECTED_MODULE] mkCore( Core );
49
50 // Instantiate the modules
51
52 Proc proc <- mkProc();
53 ICache#(InstReq,InstResp) icache <- mkInstCache();
54 DCache#(DataReq,DataResp) dcache <- mkDataCache();
55 MemArb marb <- mkMemArb();
56
57 // Internal connections
58
59 mkConnection( proc.statsEn_get, icache.statsEn_put );
60 mkConnection( proc.statsEn_get, dcache.statsEn_put );
61 mkConnection( proc.imem_client, icache.proc_server );
62 mkConnection( proc.dmem_client, dcache.proc_server );
63 mkConnection( icache.mmem_client, marb.cache0_server );
64 mkConnection( dcache.mmem_client, marb.cache1_server );
65
66 // Methods
67
68 interface mmem_client = marb.mmem_client;
69
70 endmodule