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comparison modules/bluespec/Pygar/core/Core.bsv @ 8:74716e9a81cc pygar svn.9

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[svn r9] Pygar now has the proper directory structure to play nicely with awb. Also, the apm file for audio-core willcompile successfully.
author rlm
date Fri, 23 Apr 2010 02:32:05 -0400
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7:7393cd19371e 8:74716e9a81cc
1 // The MIT License
2
3 // Copyright (c) 2009 Massachusetts Institute of Technology
4
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
11
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
14
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
22
23 import Connectable::*;
24 import GetPut::*;
25 import ClientServer::*;
26
27 import DataCacheBlocking::*;
28 import InstCacheBlocking::*;
29 import Processor::*;
30 import MemArb::*;
31 import MemTypes::*;
32
33 interface CoreStats;
34 interface DCacheStats dcache;
35 interface ICacheStats icache;
36 interface ProcStats proc;
37 endinterface
38
39 interface Core;
40
41 // Interface from core to main memory
42 interface Client#(MainMemReq,MainMemResp) mmem_client;
43
44 // Statistics
45 interface CoreStats stats;
46
47 // CPU to Host
48 interface CPUToHost tohost;
49
50 endinterface
51
52 (* synthesize *)
53 module mkCore(Core);
54
55 // Instantiate the modules
56 Proc proc <- mkProc();
57 ICache#(InstReq,InstResp) icache <- mkInstCache();
58 DCache#(DataReq,DataResp) dcache <- mkDataCache();
59 MemArb marb <- mkMemArb();
60
61 // Internal connections
62 mkConnection( proc.statsEn_get, icache.statsEn_put );
63 mkConnection( proc.statsEn_get, dcache.statsEn_put );
64 mkConnection( proc.imem_client, icache.proc_server );
65 mkConnection( proc.dmem_client, dcache.proc_server );
66 mkConnection( icache.mmem_client, marb.cache0_server );
67 mkConnection( dcache.mmem_client, marb.cache1_server );
68
69 // Methods
70 interface mmem_client = marb.mmem_client;
71
72 interface CoreStats stats;
73 interface dcache = dcache.stats;
74 interface icache = icache.stats;
75 interface proc = proc.stats;
76 endinterface
77
78 interface CPUToHost tohost = proc.tohost;
79
80 endmodule
81