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comparison modules/bluespec/Pygar/core/olaCore.bsv @ 13:6d461680c6d9 pygar svn.14

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[svn r14] more stuff
author punk
date Tue, 27 Apr 2010 09:03:28 -0400
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12:394aa40fd812 13:6d461680c6d9
1 // The MIT License
2
3 // Copyright (c) 2009 Massachusetts Institute of Technology
4
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
11
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
14
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
22
23 import Connectable::*;
24 import GetPut::*;
25 import ClientServer::*;
26
27 import DataCacheBlocking::*;
28 import InstCacheBlocking::*;
29 import Processor::*;
30 import MemArb::*;
31 import MemTypes::*;
32
33 `include "asim/provides/data_cache.bsh"
34 `include "asim/provides/instruction_cache.bsh"
35 `include "asim/provides/processor_library.bsh"
36
37 //interface CoreStats;
38 // interface DCacheStats dcache;
39 //interface ICacheStats icache;
40 //interface ProcStats proc;
41 //endinterface
42
43 interface Core;
44
45 // Interface from core to main memory
46 interface Client#(MainMemReq,MainMemResp) mmem_client;
47
48 // Statistics
49 // interface CoreStats stats;
50
51 // CPU to Host
52 interface CPUToHost tohost;
53
54 // Interface to Audio Pipeline
55 interface Audio audio;
56
57 endinterface
58
59 (* synthesize *)
60 module mkCore(Core);
61
62 // Instantiate the modules
63 Proc proc <- mkProc();
64 ICache#(InstReq,InstResp) icache <- mkInstCache();
65 DCache#(DataReq,DataResp) dcache <- mkDataCache();
66 MemArb marb <- mkMemArb();
67
68 // Internal connections
69 mkConnection( proc.statsEn_get, icache.statsEn_put );
70 mkConnection( proc.statsEn_get, dcache.statsEn_put );
71 mkConnection( proc.imem_client, icache.proc_server );
72 mkConnection( proc.dmem_client, dcache.proc_server );
73 mkConnection( icache.mmem_client, marb.cache0_server );
74 mkConnection( dcache.mmem_client, marb.cache1_server );
75
76 // Methods
77 interface mmem_client = marb.mmem_client;
78
79 // interface CoreStats stats;
80 // interface dcache = dcache.stats;
81 // interface icache = icache.stats;
82 // interface proc = proc.stats;
83 // endinterface
84
85 interface CPUToHost tohost = proc.tohost;
86
87 interface Audio audio = proc.audio;
88
89 endmodule
90