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comparison modules/bluespec/Pygar/core/audioCorePipeline.bsv~ @ 13:6d461680c6d9 pygar svn.14

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[svn r14] more stuff
author punk
date Tue, 27 Apr 2010 09:03:28 -0400
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children a1833d9f6e3d
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12:394aa40fd812 13:6d461680c6d9
1 // The MIT License
2
3 // Copyright (c) 2009 Massachusetts Institute of Technology
4
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
11
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
14
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
22
23 // Author: Kermin Fleming kfleming@mit.edu
24
25 import Connectable::*;
26 import GetPut::*;
27 import ClientServer::*;
28 import FIFO::*;
29
30 //AWB includes
31 `include "asim/provides/low_level_platform_interface.bsh"
32 `include "asim/provides/soft_connections.bsh"
33 `include "asim/provides/common_services.bsh"
34
35 //Local includes
36 `include "asim/provides/audio_processor_types.bsh" //provides Audio Pipeline interface
37 `include "asim/provides/core.bsh"
38
39 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
40 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
41
42 module [CONNECTED_MODULE] mkConnectedApplication ();
43 Core core <- mkCore;
44 Reg#(int) cycle <- mkReg(0);
45
46 //External memory
47 // I'm not comfortable assuming that the memory subsystem is in order
48 // So I'll insert a completion buffer here.
49 ClientStub_PROCESSORSYSTEMRRR client_stub <- mkClientStub_PROCESSORSYSTEMRRR();
50 // Make this big enough so that several outstanding requests may be supported
51 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
52
53 // this is for the tracing
54 rule printCycles;
55 cycle <= cycle+1;
56 $fdisplay(stderr, " => Cycle = %d", cycle);
57 endrule
58
59 rule sendMemReq;
60 let coreReq <- core.mmem_client.request.get;
61 case (coreReq) matches
62 tagged LoadReq .load: begin
63 //Allocate ROB space
64 client_stub.makeRequest_MemoryRequestLoad(load.addr);
65 tags.enq(load.tag);
66 end
67 tagged StoreReq .store: begin
68 client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
69 end
70 endcase
71 endrule
72
73 rule receiveMemResp;
74 let memResp <- client_stub.getResponse_MemoryRequestLoad();
75 tags.deq;
76 core.mmem_client.response.put(tagged LoadResp {data:memResp,
77 tag: tags.first});
78 endrule
79
80 // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together.
81
82 rule feedOutput;
83 let pipelineData <- core.sampleOutput.get();
84 AudioProcessorControl endOfFileTag = EndOfFile;
85 AudioProcessorControl sampleTag = Data;
86
87 case (pipelineData) matches
88 tagged EndOfFile: client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
89 tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)),
90 zeroExtend(pack(sample)));
91 endcase
92 endrule
93
94 endmodule