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comparison modules/bluespec/Pygar/lab4/BRegFile.bsv @ 60:6179c07c21d7 pygar svn.61

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[svn r61] synthesis boundaries
author punk
date Mon, 10 May 2010 20:29:20 -0400
parents 92041177735c
children 90fa9b289aab
comparison
equal deleted inserted replaced
59:92041177735c 60:6179c07c21d7
14 interface BRegFile #(type index_t, type data_t); 14 interface BRegFile #(type index_t, type data_t);
15 method Action upd(index_t addr, data_t data); 15 method Action upd(index_t addr, data_t data);
16 method data_t sub(index_t addr); 16 method data_t sub(index_t addr);
17 endinterface 17 endinterface
18 18
19
20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)
21 (* synthesize *)
19 module mkBRegFile(RegFile#(index_t, data_t)) 22 module mkBRegFile(RegFile#(index_t, data_t))
20 provisos (Bits#(index_t, size_index), 23 provisos (Bits#(index_t, size_index),
21 Bits#(data_t, size_data), 24 Bits#(data_t, size_data),
22 Eq#(index_t), 25 Eq#(index_t),
23 Bounded#(index_t) ); 26 Bounded#(index_t) );