comparison modules/bluespec/Pygar/core/Processor.bsv @ 11:50af57801d6e pygar svn.12

[svn r12] working on getting audio pipe processor working
author punk
date Sun, 25 Apr 2010 08:31:47 -0400
parents 74716e9a81cc
children 394aa40fd812
comparison
equal deleted inserted replaced
10:295314b16220 11:50af57801d6e
28 import FIFO::*; 28 import FIFO::*;
29 import FIFOF::*; 29 import FIFOF::*;
30 import SFIFO::*; 30 import SFIFO::*;
31 import RWire::*; 31 import RWire::*;
32 32
33 import Trace::*;
33 import BFIFO::*; 34 import BFIFO::*;
34 import MemTypes::*; 35 import MemTypes::*;
35 import ProcTypes::*; 36 import ProcTypes::*;
36 import BRegFile::*; 37 import BRegFile::*;
37 import BranchPred::*; 38 import BranchPred::*;
38 //import PathTypes::*; This is only there to force the debugging 39 //import PathTypes::*; This is only there to force the debugging
39 40
40 import Trace::*;
41
42 //AWB includes 41 //AWB includes
43 `include "asim/provides/low_level_platform_interface.bsh" 42 `include "asim/provides/low_level_platform_interface.bsh"
44 `include "asim/provides/soft_connections.bsh" 43 `include "asim/provides/soft_connections.bsh"
45 `include "asim/provides/common_services.bsh" 44 `include "asim/provides/common_services.bsh"
46 45
47 // Local includes 46 // Local includes
48 `include "asim/provides/processor_library.bsh" 47 //`include "asim/provides/processor_library.bsh" (included above directly)
49 `include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh" 48 `include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh"
50 `include "asim/provides/common_services.bsh" 49 `include "asim/provides/common_services.bsh"
51 `include "asim/dict/STATS_PROCESSOR.bsh" 50 `include "asim/dict/STATS_PROCESSOR.bsh"
52 51
53 interface ProcStats; 52 // Local includes. Look for the correspondingly named .awb files
54 interface Get#(Stat) num_cycles; 53 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
55 interface Get#(Stat) num_inst; 54 // to find the actual Bluespec files which are used to generate
56 endinterface 55 // these includes. These files are specific to this audio processing
56 // pipeline
57
58 `include "asim/provides/audio_processor_types.bsh"
57 59
58 interface CPUToHost; 60 interface CPUToHost;
59 method Bit#(32) cpuToHost(int req); 61 method Bit#(32) cpuToHost(int req);
60 endinterface 62 endinterface
61 63
66 interface Client#(InstReq,InstResp) imem_client; 68 interface Client#(InstReq,InstResp) imem_client;
67 69
68 // Interface for enabling/disabling statistics on the rest of the core 70 // Interface for enabling/disabling statistics on the rest of the core
69 interface Get#(Bool) statsEn_get; 71 interface Get#(Bool) statsEn_get;
70 72
71 // Interface for collecting statistics.
72 interface ProcStats stats;
73
74 // Interface to host 73 // Interface to host
75 interface CPUToHost tohost; 74 interface CPUToHost tohost;
76 75
76 // Interface to Audio Pipeline
77 interface Audio audio;
78
77 endinterface 79 endinterface
78 80
81 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
82 interface Audio;
83 interface Put#(AudioProcessorUnit) audioSampleInput;
84 interface Get#(AudioProcessorUnit) audioSampleOutput;
85 endinterface
79 86
80 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); 87 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
81 88
82 //----------------------------------------------------------- 89 //-----------------------------------------------------------
83 // Register file module 90 // Register file module
248 FIFO#(InstResp) instRespQ <- mkFIFO(); 255 FIFO#(InstResp) instRespQ <- mkFIFO();
249 256
250 FIFO#(DataReq) dataReqQ <- mkBFIFO1(); 257 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
251 FIFO#(DataResp) dataRespQ <- mkFIFO(); 258 FIFO#(DataResp) dataRespQ <- mkFIFO();
252 259
260 // Audio I/O
261 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
262 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
263
264
265 // Statistics state (2010)
266 // Reg#(Stat) num_cycles <- mkReg(0);
267 // Reg#(Stat) num_inst <- mkReg(0);
268
269 //Or:
253 // Statistics state 270 // Statistics state
254 Reg#(Stat) num_cycles <- mkReg(0); 271 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
255 Reg#(Stat) num_inst <- mkReg(0); 272 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
256
257 //Or:
258 // Statistics state
259 //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
260 //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
261 273
262 //----------------------------------------------------------- 274 //-----------------------------------------------------------
263 // Rules 275 // Rules
264 276
265 (* descending_urgency = "exec, pcgen" *) 277 (* descending_urgency = "exec, pcgen" *)
513 end 525 end
514 else 526 else
515 pcQ.deq(); 527 pcQ.deq();
516 528
517 if ( cp0_statsEn ) 529 if ( cp0_statsEn )
518 num_inst <= num_inst+1; 530 num_inst.incr();
519 531
520 endrule 532 endrule
521 533
522 rule writeback; // ( stage == Writeback ); 534 rule writeback; // ( stage == Writeback );
523 traceTiny("mkProc", "writeback","W"); 535 traceTiny("mkProc", "writeback","W");
539 551
540 endrule 552 endrule
541 553
542 rule inc_num_cycles; 554 rule inc_num_cycles;
543 if ( cp0_statsEn ) 555 if ( cp0_statsEn )
544 num_cycles <= num_cycles+1; 556 num_cycles.incr();
545 endrule 557 endrule
546 // THis rule breaks things 558
547 // rule handleCPUToHost; 559 (* conservative_implicit_conditions *)
548 // let req <- server_stub.acceptRequest_ReadCPUToHost(); 560 rule handleCPUToHost;
549 // case (req) 561 let req <- server_stub.acceptRequest_ReadCPUToHost();
550 // 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); 562 case (req)
551 // 1: server_stub.sendResponse_ReadCPUToHost(pc); 563 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
552 // 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage))); 564 1: server_stub.sendResponse_ReadCPUToHost(pc);
553 // endcase 565 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
554 // endrule 566 endcase
555 //----------------------------------------------------------- 567 endrule
556 // My Adds 568
557 //----------------------------------------------------------- 569 // for now, we don't do anything.
570 rule connectAudioReqResp;
571 $display("FIR copies a data");
572 outAudioFifo.enq(inAudioFifo.first);
573 outAudioFifo.deq;
574 endrule
558 575
559 //----------------------------------------------------------- 576 //-----------------------------------------------------------
560 // Methods 577 // Methods
561 578
562 interface Client imem_client; 579 interface Client imem_client;
568 interface Get request = toGet(dataReqQ); 585 interface Get request = toGet(dataReqQ);
569 interface Put response = toPut(dataRespQ); 586 interface Put response = toPut(dataRespQ);
570 endinterface 587 endinterface
571 588
572 interface Get statsEn_get = toGet(asReg(cp0_statsEn)); 589 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
573
574 interface ProcStats stats;
575 interface Get num_cycles = toGet(asReg(num_cycles));
576 interface Get num_inst = toGet(asReg(num_inst));
577 endinterface
578 590
579 interface CPUToHost tohost; 591 interface CPUToHost tohost;
580 method Bit#(32) cpuToHost(int req); 592 method Bit#(32) cpuToHost(int req);
581 return (case (req) 593 return (case (req)
582 0: cp0_tohost; 594 0: cp0_tohost;
584 2: zeroExtend(pack(stage)); 596 2: zeroExtend(pack(stage));
585 endcase); 597 endcase);
586 endmethod 598 endmethod
587 endinterface 599 endinterface
588 600
601 interface Audio audio;
602 interface audioSampleInput = fifoToPut(inAudioFifo);
603 interface audioSampleOutput = fifoToGet(outAudioFifo);
604 endinterface
605
606
589 endmodule 607 endmodule
590 608