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comparison modules/bluespec/Pygar/core/#Processor.bsv# @ 50:2b18894f75e2 pygar svn.51

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[svn r51] fixed processor- it works
author punk
date Wed, 05 May 2010 15:19:32 -0400
parents 99519a031813
children
comparison
equal deleted inserted replaced
49:61f6267cb3db 50:2b18894f75e2
78 // Interface to Audio Pipeline 78 // Interface to Audio Pipeline
79 interface Get#(AudioProcessorUnit) sampleOutput; 79 interface Get#(AudioProcessorUnit) sampleOutput;
80 interface Put#(AudioProcessorUnit) sampleInput; 80 interface Put#(AudioProcessorUnit) sampleInput;
81 81
82 endinterface 82 endinterface
83
84 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
85 //interface AudioOut;
86 // interface Get#(AudioProcessorUnit) audioSampleOutput;
87 //endinterface
88
89 //interface AudioIn;
90 // interface Put#(AudioProcessorUnit) audioSampleInput;
91 //endinterface
92 83
93 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); 84 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
94 85
95 //----------------------------------------------------------- 86 //-----------------------------------------------------------
96 // Register file module 87 // Register file module
259 250
260 FIFO#(DataReq) dataReqQ <- mkBFIFO1(); 251 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
261 FIFO#(DataResp) dataRespQ <- mkFIFO(); 252 FIFO#(DataResp) dataRespQ <- mkFIFO();
262 253
263 // Audio I/O 254 // Audio I/O
264 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO; 255 FIFO#(AudioProcessorUnit) inAudioFifo <- mkSizedFIFO(512);
265 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO; 256 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
266 257
267 258
268 // Statistics state (2010) 259 // Statistics state (2010)
269 // Reg#(Stat) num_cycles <- mkReg(0); 260 // Reg#(Stat) num_cycles <- mkReg(0);
463 newPC = { pc_plus4[31:28], it.target, 2'b0 }; 454 newPC = { pc_plus4[31:28], it.target, 2'b0 };
464 branchTaken = True; 455 branchTaken = True;
465 end 456 end
466 457
467 tagged JR .it : 458 tagged JR .it :
468 begin 459 begin
469 newPC = rf.rd1(it.rsrc); 460 newPC = rf.rd1(it.rsrc);
470 branchTaken = True; 461 branchTaken = True;
471 end 462 end
472 463
473 tagged JAL .it : 464 tagged JAL .it :
486 477
487 // -- Cop0 ------------------------------------------------------ 478 // -- Cop0 ------------------------------------------------------
488 479
489 tagged MTC0 .it : //Recieve things from host computer 480 tagged MTC0 .it : //Recieve things from host computer
490 begin 481 begin
491 $display( " PROCESSOR MTC0 call\n"); 482 // $display( " PROCESSOR MTC0 call\n");
492 case ( it.cop0dst ) 483 case ( it.cop0dst )
493 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); 484 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
494 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); 485 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
495 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay 486 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
496 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32 487 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32
501 end 492 end
502 493
503 //this is host stuff? 494 //this is host stuff?
504 tagged MFC0 .it : //Things out 495 tagged MFC0 .it : //Things out
505 begin 496 begin
506 $display( " PROCESSOR MFC0 call\n");
507 case ( it.cop0src ) 497 case ( it.cop0src )
508 // not actually an ALU instruction but don't have the format otherwise 498 // not actually an ALU instruction but don't have the format otherwise
509 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); 499 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
510 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); 500 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
511 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); 501 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
512 5'd25 : begin 502 5'd25 : begin
513 $display( "**** EOF Requested\n "); 503 / $display( "**** EOF Requested\n ");
514 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit 504 let sample = inAudioFifo.first();
515 cp0_audioEOF <= False; 505 case (sample) matches
506 tagged EndOfFile :
507 begin
508 $display("PROCESSOR sent toC EOF");
509 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(True)) }); // Reading clears bit
510 inAudioFifo.deq;
511 end
512 tagged Sample .data:
513 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(False)) }); // Reading clears bit
514 endcase
516 end 515 end
517 5'd28 : begin 516 5'd28 : begin
518 $display( "***** Reqesting Sample \n"); 517 $display( "***** Reqesting Sample \n");
519 let sample = inAudioFifo.first(); // is this going to cause perf. delay? 518 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
520 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF 519 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
521 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack? 520 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
522 else $display ( "Audio File EOF Reached. Invalid sample request."); 521 else $display ( "Audio File EOF Reached. Invalid sample request.");
523 inAudioFifo.deq(); 522 inAudioFifo.deq();
524 end 523 end
525 default : 524 default :
526 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); 525 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
574 rule inc_num_cycles; 573 rule inc_num_cycles;
575 if ( cp0_statsEn ) 574 if ( cp0_statsEn )
576 num_cycles.incr(); 575 num_cycles.incr();
577 endrule 576 endrule
578 577
579 578 /*
580 // for now, we don't do anything. 579 // for now, we don't do anything.
581 // rule connectAudioReqResp; 580 rule connectAudioReqResp;
582 // $display("rlm: PROCESSOR copies a datum\n"); 581 $display("rlm: PROCESSOR copies a datum\n");
583 // outAudioFifo.enq(inAudioFifo.first()); 582 outAudioFifo.enq(inAudioFifo.first());
584 // inAudioFifo.deq; 583 inAudioFifo.deq;
585 // endrule 584 endrule
586 585 */
586 /*
587 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile); 587 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
588 $display (" Proc Says End Audio Flag Set "); 588 $display (" PROCESSOR End Audio Flag Set ");
589 cp0_audioEOF <= True; 589 cp0_audioEOF <= True;
590 inAudioFifo.deq; 590 inAudioFifo.deq;
591 endrule 591 endrule
592 592 */
593 rule sendAudioEnd (cp0_progComp); 593 rule sendProcEnd (cp0_progComp);
594 $display (" PROCESSOR Says Program Complete "); 594 $display (" PROCESSOR Says Program Complete ");
595 outAudioFifo.enq(tagged EndOfFile); 595 outAudioFifo.enq(tagged EndOfFile);
596 cp0_progComp <= False; //only send one. And functions to reset 596 cp0_progComp <= False; //only send one. And functions to reset
597 endrule 597 endrule
598 598