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1 // The MIT License
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2
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3 // Copyright (c) 2009 Massachusetts Institute of Technology
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4
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5 // Permission is hereby granted, free of charge, to any person obtaining a copy
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6 // of this software and associated documentation files (the "Software"), to deal
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7 // in the Software without restriction, including without limitation the rights
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8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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9 // copies of the Software, and to permit persons to whom the Software is
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10 // furnished to do so, subject to the following conditions:
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11
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12 // The above copyright notice and this permission notice shall be included in
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13 // all copies or substantial portions of the Software.
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14
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15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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21 // THE SOFTWARE.
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22
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23 import Connectable::*;
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24 import GetPut::*;
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25 import ClientServer::*;
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26 import Processor::*;
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27 import MemArb::*;
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28 import MemTypes::*;
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29
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30 //AWB includes
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31 `include "asim/provides/low_level_platform_interface.bsh"
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32 `include "asim/provides/soft_connections.bsh"
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33 `include "asim/provides/common_services.bsh"
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34
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35 // Local includes
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36 `include "asim/provides/processor_library.bsh"
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37 `include "asim/provides/processor.bsh"
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38 `include "asim/provides/audio_pipe_types.bsh"
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39
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40 interface Core;
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41
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42 // Interface from core to main memory
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43 interface Client#(MainMemReq,MainMemResp) mmem_client;
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44
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45 interface Get#(AudioProcessorUnit) sampleOutput;
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46
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47 endinterface
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48
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49 module [CONNECTED_MODULE] mkCore( Core );
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50
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51 // Instantiate the modules
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52
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53 Proc proc <- mkProc();
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54 ICache#(InstReq,InstResp) icache <- mkInstCache();
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55 DCache#(DataReq,DataResp) dcache <- mkDataCache();
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56 MemArb marb <- mkMemArb();
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57
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58 // Internal connections
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59
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60 interface sampleOutput = proc.sampleOutput;
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61
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62 endmodule
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