|
rlm@8
|
1 // The MIT License
|
|
rlm@8
|
2
|
|
rlm@8
|
3 // Copyright (c) 2009 Massachusetts Institute of Technology
|
|
rlm@8
|
4
|
|
rlm@8
|
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
rlm@8
|
6 // of this software and associated documentation files (the "Software"), to deal
|
|
rlm@8
|
7 // in the Software without restriction, including without limitation the rights
|
|
rlm@8
|
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
rlm@8
|
9 // copies of the Software, and to permit persons to whom the Software is
|
|
rlm@8
|
10 // furnished to do so, subject to the following conditions:
|
|
rlm@8
|
11
|
|
rlm@8
|
12 // The above copyright notice and this permission notice shall be included in
|
|
rlm@8
|
13 // all copies or substantial portions of the Software.
|
|
rlm@8
|
14
|
|
rlm@8
|
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
rlm@8
|
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
rlm@8
|
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
|
rlm@8
|
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
rlm@8
|
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
rlm@8
|
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
rlm@8
|
21 // THE SOFTWARE.
|
|
rlm@8
|
22
|
|
rlm@8
|
23 import Connectable::*;
|
|
rlm@8
|
24 import GetPut::*;
|
|
rlm@8
|
25 import ClientServer::*;
|
|
rlm@8
|
26 import RegFile::*;
|
|
rlm@8
|
27 import FIFO::*;
|
|
rlm@8
|
28 import FIFOF::*;
|
|
rlm@8
|
29 import RWire::*;
|
|
punk@28
|
30 import Trace::*;
|
|
rlm@8
|
31
|
|
rlm@8
|
32 // Local includes
|
|
rlm@8
|
33 `include "asim/provides/low_level_platform_interface.bsh"
|
|
rlm@8
|
34 `include "asim/provides/soft_connections.bsh"
|
|
rlm@8
|
35 `include "asim/provides/processor_library.bsh"
|
|
rlm@8
|
36 `include "asim/provides/fpga_components.bsh"
|
|
rlm@8
|
37 `include "asim/provides/common_services.bsh"
|
|
rlm@8
|
38
|
|
rlm@8
|
39 interface ICache#( type req_t, type resp_t );
|
|
rlm@8
|
40
|
|
rlm@8
|
41 // Interface from processor to cache
|
|
rlm@8
|
42 interface Server#(req_t,resp_t) proc_server;
|
|
rlm@8
|
43
|
|
rlm@8
|
44 // Interface from cache to main memory
|
|
rlm@8
|
45 interface Client#(MainMemReq,MainMemResp) mmem_client;
|
|
rlm@8
|
46
|
|
rlm@8
|
47 // Interface for enabling/disabling statistics
|
|
rlm@8
|
48 interface Put#(Bool) statsEn_put;
|
|
rlm@8
|
49
|
|
rlm@8
|
50 endinterface
|
|
rlm@8
|
51
|
|
rlm@8
|
52 //----------------------------------------------------------------------
|
|
rlm@8
|
53 // Cache Types
|
|
rlm@8
|
54 //----------------------------------------------------------------------
|
|
rlm@8
|
55
|
|
rlm@8
|
56 typedef 10 CacheLineIndexSz;
|
|
rlm@8
|
57 typedef 20 CacheLineTagSz;
|
|
rlm@8
|
58 typedef 32 CacheLineSz;
|
|
rlm@8
|
59
|
|
rlm@8
|
60 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
|
|
rlm@8
|
61 typedef Bit#(CacheLineTagSz) CacheLineTag;
|
|
rlm@8
|
62 typedef Bit#(CacheLineSz) CacheLine;
|
|
rlm@8
|
63
|
|
rlm@8
|
64 typedef enum
|
|
rlm@8
|
65 {
|
|
rlm@8
|
66 Init,
|
|
rlm@8
|
67 Access,
|
|
rlm@8
|
68 Evict,
|
|
rlm@8
|
69 RefillReq,
|
|
rlm@8
|
70 RefillResp
|
|
rlm@8
|
71 }
|
|
rlm@8
|
72 CacheStage
|
|
rlm@8
|
73 deriving (Eq,Bits);
|
|
rlm@8
|
74
|
|
rlm@8
|
75 //----------------------------------------------------------------------
|
|
rlm@8
|
76 // Helper functions
|
|
rlm@8
|
77 //----------------------------------------------------------------------
|
|
rlm@8
|
78
|
|
rlm@8
|
79 function Bit#(AddrSz) getAddr( InstReq req );
|
|
rlm@8
|
80
|
|
rlm@8
|
81 Bit#(AddrSz) addr = ?;
|
|
rlm@8
|
82 case ( req ) matches
|
|
rlm@8
|
83 tagged LoadReq .ld : addr = ld.addr;
|
|
rlm@8
|
84 tagged StoreReq .st : addr = st.addr;
|
|
rlm@8
|
85 endcase
|
|
rlm@8
|
86
|
|
rlm@8
|
87 return addr;
|
|
rlm@8
|
88
|
|
rlm@8
|
89 endfunction
|
|
rlm@8
|
90
|
|
rlm@8
|
91 function CacheLineIndex getCacheLineIndex( InstReq req );
|
|
rlm@8
|
92 Bit#(AddrSz) addr = getAddr(req);
|
|
rlm@8
|
93 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
|
|
rlm@8
|
94 return index;
|
|
rlm@8
|
95 endfunction
|
|
rlm@8
|
96
|
|
rlm@8
|
97 function CacheLineTag getCacheLineTag( InstReq req );
|
|
rlm@8
|
98 Bit#(AddrSz) addr = getAddr(req);
|
|
rlm@8
|
99 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
|
|
rlm@8
|
100 return tag;
|
|
rlm@8
|
101 endfunction
|
|
rlm@8
|
102
|
|
rlm@8
|
103 function Bit#(AddrSz) getCacheLineAddr( InstReq req );
|
|
rlm@8
|
104 Bit#(AddrSz) addr = getAddr(req);
|
|
rlm@8
|
105 return ((addr >> 2) << 2);
|
|
rlm@8
|
106 endfunction
|
|
rlm@8
|
107
|
|
rlm@8
|
108 //----------------------------------------------------------------------
|
|
rlm@8
|
109 // Main module
|
|
rlm@8
|
110 //----------------------------------------------------------------------
|
|
rlm@8
|
111
|
|
punk@60
|
112 (* doc = "synthesis attribute ram_style mkInstCache distributed;" *)
|
|
punk@60
|
113 (* synthesize *)
|
|
punk@63
|
114 module mkInstCache( ICache#(InstReq,InstResp) );
|
|
rlm@8
|
115
|
|
rlm@8
|
116 //-----------------------------------------------------------
|
|
rlm@8
|
117 // State
|
|
rlm@8
|
118
|
|
rlm@8
|
119 Reg#(CacheStage) stage <- mkReg(Init);
|
|
rlm@8
|
120
|
|
rlm@8
|
121 LUTRAM#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkLUTRAMU_RegFile();
|
|
rlm@8
|
122 LUTRAM#(CacheLineIndex,CacheLine) cacheDataRam <- mkLUTRAMU_RegFile();
|
|
rlm@8
|
123
|
|
rlm@8
|
124 FIFO#(InstReq) reqQ <- mkFIFO();
|
|
rlm@8
|
125 FIFOF#(InstResp) respQ <- mkBFIFOF1();
|
|
rlm@8
|
126
|
|
rlm@8
|
127 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
|
|
rlm@8
|
128 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
|
|
rlm@8
|
129
|
|
rlm@8
|
130 Reg#(CacheLineIndex) initCounter <- mkReg(1);
|
|
rlm@8
|
131
|
|
rlm@8
|
132 // Statistics state
|
|
rlm@8
|
133
|
|
rlm@8
|
134 Reg#(Bool) statsEn <- mkReg(False);
|
|
rlm@8
|
135
|
|
rlm@49
|
136 //rlm:
|
|
rlm@49
|
137 //STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);
|
|
rlm@49
|
138 //STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);
|
|
rlm@49
|
139 //STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);
|
|
rlm@8
|
140
|
|
rlm@8
|
141 //-----------------------------------------------------------
|
|
rlm@8
|
142 // Name some wires
|
|
rlm@8
|
143
|
|
rlm@8
|
144 let req = reqQ.first();
|
|
rlm@8
|
145 let reqIndex = getCacheLineIndex(req);
|
|
rlm@8
|
146 let reqTag = getCacheLineTag(req);
|
|
rlm@8
|
147 let reqCacheLineAddr = getCacheLineAddr(req);
|
|
rlm@8
|
148 let refill = mainMemRespQ.first();
|
|
rlm@8
|
149
|
|
rlm@8
|
150 //-----------------------------------------------------------
|
|
rlm@8
|
151 // Initialize
|
|
rlm@8
|
152
|
|
rlm@8
|
153 rule init ( stage == Init );
|
|
rlm@8
|
154 traceTiny("mkInstCacheBlocking", "stage","i");
|
|
rlm@8
|
155 initCounter <= initCounter + 1;
|
|
rlm@8
|
156 cacheTagRam.upd(initCounter,Invalid);
|
|
rlm@8
|
157 if ( initCounter == 0 )
|
|
rlm@8
|
158 stage <= Access;
|
|
rlm@8
|
159 endrule
|
|
rlm@8
|
160
|
|
rlm@8
|
161 //-----------------------------------------------------------
|
|
rlm@8
|
162 // Cache access rule
|
|
rlm@8
|
163
|
|
rlm@8
|
164 rule access ( (stage == Access) && respQ.notFull() );
|
|
rlm@8
|
165
|
|
rlm@8
|
166 // Statistics
|
|
rlm@49
|
167 //rlm:
|
|
rlm@49
|
168 // if ( statsEn )
|
|
rlm@49
|
169 // num_accesses.incr();
|
|
rlm@8
|
170
|
|
rlm@8
|
171 // Check tag and valid bit to see if this is a hit or a miss
|
|
rlm@8
|
172
|
|
rlm@8
|
173 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
|
|
rlm@8
|
174
|
|
rlm@8
|
175 // Handle cache hits ...
|
|
rlm@8
|
176
|
|
rlm@8
|
177 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
|
|
rlm@8
|
178 begin
|
|
rlm@8
|
179 traceTiny("mkInstCacheBlocking", "hitMiss","h");
|
|
rlm@8
|
180 reqQ.deq();
|
|
rlm@8
|
181
|
|
rlm@8
|
182 case ( req ) matches
|
|
rlm@8
|
183
|
|
rlm@8
|
184 tagged LoadReq .ld :
|
|
rlm@8
|
185 respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } );
|
|
rlm@8
|
186
|
|
rlm@8
|
187 tagged StoreReq .st :
|
|
rlm@8
|
188 $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" );
|
|
rlm@8
|
189
|
|
rlm@8
|
190 endcase
|
|
rlm@8
|
191
|
|
rlm@8
|
192 end
|
|
rlm@8
|
193
|
|
rlm@8
|
194 // Handle cache misses - since lines in instruction cache are
|
|
rlm@8
|
195 // never dirty we can always immediately issue a refill request
|
|
rlm@8
|
196
|
|
rlm@8
|
197 else
|
|
rlm@8
|
198 begin
|
|
rlm@8
|
199 traceTiny("mkInstCacheBlocking", "hitMiss","m");
|
|
rlm@49
|
200 //rlm:
|
|
rlm@49
|
201 //if ( statsEn )
|
|
rlm@49
|
202 //num_misses.incr();
|
|
rlm@49
|
203 //if ( statsEn )
|
|
rlm@49
|
204 //if ( isJust(cacheLineTag) )
|
|
rlm@49
|
205 //num_evictions.incr();
|
|
rlm@8
|
206
|
|
rlm@8
|
207 MainMemReq rfReq
|
|
rlm@8
|
208 = LoadReq { tag : 0,
|
|
rlm@8
|
209 addr : reqCacheLineAddr };
|
|
rlm@8
|
210
|
|
rlm@8
|
211 mainMemReqQ.enq(rfReq);
|
|
rlm@8
|
212 stage <= RefillResp;
|
|
rlm@8
|
213 end
|
|
rlm@8
|
214
|
|
rlm@8
|
215 endrule
|
|
rlm@8
|
216
|
|
rlm@8
|
217 //-----------------------------------------------------------
|
|
rlm@8
|
218 // Refill response rule
|
|
rlm@8
|
219
|
|
rlm@8
|
220 rule refillResp ( stage == RefillResp );
|
|
rlm@8
|
221 traceTiny("mkInstCacheBlocking", "stage","R");
|
|
rlm@8
|
222 traceTiny("mkInstCacheBlocking", "refill",refill);
|
|
rlm@8
|
223
|
|
rlm@8
|
224 // Write the new data into the cache and update the tag
|
|
rlm@8
|
225
|
|
rlm@8
|
226 mainMemRespQ.deq();
|
|
rlm@8
|
227 case ( mainMemRespQ.first() ) matches
|
|
rlm@8
|
228
|
|
rlm@8
|
229 tagged LoadResp .ld :
|
|
rlm@8
|
230 begin
|
|
rlm@8
|
231 cacheTagRam.upd(reqIndex,Valid(reqTag));
|
|
rlm@8
|
232 cacheDataRam.upd(reqIndex,ld.data);
|
|
rlm@8
|
233 end
|
|
rlm@8
|
234
|
|
rlm@8
|
235 tagged StoreResp .st :
|
|
rlm@8
|
236 noAction;
|
|
rlm@8
|
237
|
|
rlm@8
|
238 endcase
|
|
rlm@8
|
239
|
|
rlm@8
|
240 stage <= Access;
|
|
rlm@8
|
241 endrule
|
|
rlm@8
|
242
|
|
rlm@8
|
243 //-----------------------------------------------------------
|
|
rlm@8
|
244 // Methods
|
|
rlm@8
|
245
|
|
rlm@8
|
246 interface Client mmem_client;
|
|
rlm@8
|
247 interface Get request = fifoToGet(mainMemReqQ);
|
|
rlm@8
|
248 interface Put response = fifoToPut(mainMemRespQ);
|
|
rlm@8
|
249 endinterface
|
|
rlm@8
|
250
|
|
rlm@8
|
251 interface Server proc_server;
|
|
rlm@8
|
252 interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",fifoToPut(reqQ));
|
|
rlm@8
|
253 interface Get response = traceGet("mkInstCacheBlocking", "respTiny",fifofToGet(respQ));
|
|
rlm@8
|
254 endinterface
|
|
rlm@8
|
255
|
|
rlm@8
|
256 interface Put statsEn_put = regToPut(statsEn);
|
|
rlm@8
|
257
|
|
rlm@8
|
258 endmodule
|
|
rlm@8
|
259
|
