annotate modules/bluespec/Pygar/lab4/core.awb @ 65:cf8bb3038cbd pygar svn.66

[svn r66] sim passes
author punk
date Tue, 11 May 2010 09:05:22 -0400
parents 50af57801d6e
children
rev   line source
rlm@8 1 %name Simple Processor Core
rlm@8 2 %desc Instantiates a processor, some caches, and a memory arbiter
rlm@8 3
rlm@8 4 %provides core
rlm@8 5
rlm@8 6 %requires mem_arb
rlm@8 7 %requires instruction_cache
rlm@8 8 %requires data_cache
rlm@8 9 %requires processor
rlm@8 10 %requires processor_library
rlm@8 11
punk@11 12 %attributes PYGAR
rlm@8 13
rlm@8 14 %public Core.bsv
rlm@8 15
rlm@8 16