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annotate modules/bluespec/Pygar/lab4/ProcessorSystemRRR.rrr @ 65:cf8bb3038cbd pygar svn.66

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[svn r66] sim passes
author punk
date Tue, 11 May 2010 09:05:22 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 service PROCESSORSYSTEMRRR
rlm@8 2 {
rlm@8 3 server hw (bsv, connection) <- sw (cpp, method)
rlm@8 4 {
rlm@8 5 method ReadCPUToHost (out UINT32[32] regValue, in UINT32[32] dummy);
rlm@8 6 method WriteHostToCPU (in UINT32[32] regValue);
rlm@8 7 };
rlm@8 8
rlm@8 9 server sw (cpp, method) <- hw (bsv, connection)
rlm@8 10 {
rlm@8 11 method MemoryRequestLoad (in UINT32[32] address, out UINT32[32] value);
rlm@8 12 method MemoryRequestStore (in UINT32[32] address, in UINT32[32] value);
rlm@8 13 };
rlm@8 14
rlm@8 15 };