annotate modules/bluespec/Pygar/lab4/ProcessorSystem.bsv @ 65:cf8bb3038cbd pygar svn.66

[svn r66] sim passes
author punk
date Tue, 11 May 2010 09:05:22 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 // The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@8 23 import Connectable::*;
rlm@8 24 import GetPut::*;
rlm@8 25 import ClientServer::*;
rlm@8 26 import FIFO::*;
rlm@8 27 import SpecialFIFOs::*;
rlm@8 28
rlm@8 29 //AWB includes
rlm@8 30 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8 31 `include "asim/provides/soft_connections.bsh"
rlm@8 32 `include "asim/provides/common_services.bsh"
rlm@8 33
rlm@8 34
rlm@8 35 // Local includes
rlm@8 36 `include "asim/provides/core.bsh"
rlm@8 37 `include "asim/provides/processor_library.bsh"
rlm@8 38 `include "asim/provides/processor_library.bsh"
rlm@8 39 `include "asim/provides/fpga_components.bsh"
rlm@8 40 `include "asim/rrr/remote_client_stub_PROCESSORSYSTEMRRR.bsh"
rlm@8 41
rlm@8 42 module [CONNECTED_MODULE] mkConnectedApplication ();
rlm@8 43
rlm@8 44 Core core <- mkCore;
rlm@8 45 Reg#(int) cycle <- mkReg(0);
rlm@8 46
rlm@8 47 //External memory
rlm@8 48 // I'm not comfortable assuming that the memory subsystem is in order
rlm@8 49 // So I'll insert a completion buffer here.
rlm@8 50 ClientStub_PROCESSORSYSTEMRRR client_stub <- mkClientStub_PROCESSORSYSTEMRRR();
rlm@8 51 // Make this big enough so that several outstanding requests may be supported
rlm@8 52 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
rlm@8 53
rlm@8 54 // this is for the tracing
rlm@8 55 rule printCycles;
rlm@8 56 cycle <= cycle+1;
rlm@8 57 $fdisplay(stderr, " => Cycle = %d", cycle);
rlm@8 58 endrule
rlm@8 59
rlm@8 60
rlm@8 61 rule sendMemReq;
rlm@8 62 let coreReq <- core.mmem_client.request.get;
rlm@8 63 case (coreReq) matches
rlm@8 64 tagged LoadReq .load: begin
rlm@8 65 //Allocate ROB space
rlm@8 66 client_stub.makeRequest_MemoryRequestLoad(load.addr);
rlm@8 67 tags.enq(load.tag);
rlm@8 68 end
rlm@8 69 tagged StoreReq .store: begin
rlm@8 70 client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
rlm@8 71 end
rlm@8 72 endcase
rlm@8 73 endrule
rlm@8 74
rlm@8 75 rule receiveMemResp;
rlm@8 76 let memResp <- client_stub.getResponse_MemoryRequestLoad();
rlm@8 77 tags.deq;
rlm@8 78 core.mmem_client.response.put(tagged LoadResp {data:memResp,
rlm@8 79 tag: tags.first});
rlm@8 80 endrule
rlm@8 81
rlm@8 82 endmodule