annotate modules/bluespec/Pygar/lab4/BRegFile.bsv @ 65:cf8bb3038cbd pygar svn.66

[svn r66] sim passes
author punk
date Tue, 11 May 2010 09:05:22 -0400
parents 1d5cbb5343d2
children
rev   line source
rlm@8 1 import RegFile::*;
rlm@8 2 import RWire::*;
rlm@8 3 import ProcTypes::*;
rlm@8 4
punk@58 5 `include "asim/provides/low_level_platform_interface.bsh"
punk@58 6 `include "asim/provides/soft_connections.bsh"
punk@58 7 `include "asim/provides/fpga_components.bsh"
punk@58 8 `include "asim/provides/common_services.bsh"
punk@58 9
rlm@8 10 //-----------------------------------------------------------
rlm@8 11 // Register file module
rlm@8 12 //-----------------------------------------------------------
rlm@8 13
punk@63 14 interface BRegFile;
punk@62 15 method Action wr( Rindx rindx, Bit#(32) data );
punk@63 16 method ActionValue#( Bit#(32)) rd1( Rindx rindx );
punk@63 17 method ActionValue#( Bit#(32)) rd2( Rindx rindx );
rlm@8 18 endinterface
rlm@8 19
punk@60 20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)
punk@60 21 (* synthesize *)
punk@63 22 module mkBRegFile(BRegFile);
rlm@8 23
punk@63 24 LUTRAM#(Rindx, Bit#(32)) rf <- mkLUTRAMU_RegFile();
punk@63 25 RWire#(Tuple2#(Rindx, Bit#(32))) rw <-mkRWire();
rlm@8 26
punk@62 27 method Action wr( Rindx rindx, Bit#(32) data );
punk@62 28 rf.upd( rindx, data );
punk@63 29 rw.wset(tuple2(rindx,data));
rlm@8 30 endmethod
rlm@8 31
punk@63 32 method ActionValue#(Bit#(32)) rd1 (Rindx r);
punk@62 33 if (r == 0) return 0;
punk@62 34 else begin
punk@62 35 case (rw.wget()) matches
punk@62 36 tagged Valid {.wr, .d} :
punk@62 37 return (wr == r) ? d : rf.sub(r);
punk@62 38 tagged Invalid : return rf.sub(r);
punk@62 39 endcase
punk@62 40 end
punk@62 41 endmethod
punk@62 42
punk@63 43 method ActionValue#(Bit#(32)) rd2 (Rindx r);
punk@62 44 if (r == 0) return 0;
punk@62 45 else begin
punk@62 46 case (rw.wget()) matches
punk@62 47 tagged Valid {.wr, .d} :
punk@62 48 return (wr == r) ? d : rf.sub(r);
punk@62 49 tagged Invalid : return rf.sub(r);
punk@62 50 endcase
punk@62 51 end
rlm@8 52 endmethod
rlm@8 53
rlm@8 54 endmodule