annotate modules/bluespec/Pygar/lab4/BranchPred.bsv @ 60:6179c07c21d7
pygar svn.61
[svn r61] synthesis boundaries
| author |
punk |
| date |
Mon, 10 May 2010 20:29:20 -0400 |
| parents |
74716e9a81cc |
| children |
|
| rev |
line source |
|
rlm@8
|
1 import RegFile::*;
|
|
rlm@8
|
2 import ProcTypes::*;
|
|
rlm@8
|
3 import FIFO::*;
|
|
rlm@8
|
4
|
|
rlm@8
|
5 typedef Maybe#(Addr) BrPred;
|
|
rlm@8
|
6 typedef Bit#(4) BPindx;
|
|
rlm@8
|
7
|
|
rlm@8
|
8 typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq);
|
|
rlm@8
|
9
|
|
rlm@8
|
10 typedef union tagged
|
|
rlm@8
|
11 {
|
|
rlm@8
|
12 BrPair Valid;
|
|
rlm@8
|
13 void Invalid;
|
|
rlm@8
|
14 } CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values.
|
|
rlm@8
|
15
|
|
rlm@8
|
16 interface BranchPred;
|
|
rlm@8
|
17 method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition
|
|
rlm@8
|
18 method Action upd(Addr pres, Addr next);
|
|
rlm@8
|
19 endinterface
|
|
rlm@8
|
20
|
|
rlm@8
|
21 module mkBranchPred(BranchPred);
|
|
rlm@8
|
22
|
|
rlm@8
|
23 //state variables
|
|
rlm@8
|
24 RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx)
|
|
rlm@8
|
25
|
|
rlm@8
|
26 method Action upd(Addr pres, Addr next);
|
|
rlm@8
|
27 BrPair brp;
|
|
rlm@8
|
28 brp = BrPair {brpc:pres, nextpc:next};
|
|
rlm@8
|
29 bcache.upd(pres[5:2], tagged Valid brp);
|
|
rlm@8
|
30 endmethod
|
|
rlm@8
|
31
|
|
rlm@8
|
32 method BrPred get(Addr prespc);
|
|
rlm@8
|
33 BPindx rd = prespc[5:2];
|
|
rlm@8
|
34 let cbp = bcache.sub(rd);
|
|
rlm@8
|
35 if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches
|
|
rlm@8
|
36 return tagged Valid bp.nextpc;
|
|
rlm@8
|
37 else return Invalid;
|
|
rlm@8
|
38 endmethod
|
|
rlm@8
|
39
|
|
rlm@8
|
40 endmodule
|
|
rlm@8
|
41
|
