annotate modules/bluespec/Pygar/core/InstCacheBlocking.d @ 13:6d461680c6d9 pygar svn.14

[svn r14] more stuff
author punk
date Tue, 27 Apr 2010 09:03:28 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 // The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@8 23 import Connectable::*;
rlm@8 24 import GetPut::*;
rlm@8 25 import ClientServer::*;
rlm@8 26 import RegFile::*;
rlm@8 27 import FIFO::*;
rlm@8 28 import FIFOF::*;
rlm@8 29 import RWire::*;
rlm@8 30
rlm@8 31 import BFIFO::*;
rlm@8 32 import MemTypes::*;
rlm@8 33 import ProcTypes::*;
rlm@8 34 import Trace::*;
rlm@8 35
rlm@8 36 interface ICacheStats;
rlm@8 37 interface Get#(Stat) num_accesses;
rlm@8 38 interface Get#(Stat) num_misses;
rlm@8 39 interface Get#(Stat) num_evictions;
rlm@8 40 endinterface
rlm@8 41
rlm@8 42 interface ICache#( type req_t, type resp_t );
rlm@8 43
rlm@8 44 // Interface from processor to cache
rlm@8 45 interface Server#(req_t,resp_t) proc_server;
rlm@8 46
rlm@8 47 // Interface from cache to main memory
rlm@8 48 interface Client#(MainMemReq,MainMemResp) mmem_client;
rlm@8 49
rlm@8 50 // Interface for enabling/disabling statistics
rlm@8 51 interface Put#(Bool) statsEn_put;
rlm@8 52
rlm@8 53 // Interface for collecting statistics
rlm@8 54 interface ICacheStats stats;
rlm@8 55
rlm@8 56 endinterface
rlm@8 57
rlm@8 58 //----------------------------------------------------------------------
rlm@8 59 // Cache Types
rlm@8 60 //----------------------------------------------------------------------
rlm@8 61
rlm@8 62 typedef 10 CacheLineIndexSz;
rlm@8 63 typedef 20 CacheLineTagSz;
rlm@8 64 typedef 32 CacheLineSz;
rlm@8 65
rlm@8 66 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
rlm@8 67 typedef Bit#(CacheLineTagSz) CacheLineTag;
rlm@8 68 typedef Bit#(CacheLineSz) CacheLine;
rlm@8 69
rlm@8 70 typedef enum
rlm@8 71 {
rlm@8 72 Init,
rlm@8 73 Access,
rlm@8 74 Evict,
rlm@8 75 RefillReq,
rlm@8 76 RefillResp
rlm@8 77 }
rlm@8 78 CacheStage
rlm@8 79 deriving (Eq,Bits);
rlm@8 80
rlm@8 81 //----------------------------------------------------------------------
rlm@8 82 // Helper functions
rlm@8 83 //----------------------------------------------------------------------
rlm@8 84
rlm@8 85 function Bit#(AddrSz) getAddr( InstReq req );
rlm@8 86
rlm@8 87 Bit#(AddrSz) addr = ?;
rlm@8 88 case ( req ) matches
rlm@8 89 tagged LoadReq .ld : addr = ld.addr;
rlm@8 90 tagged StoreReq .st : addr = st.addr;
rlm@8 91 endcase
rlm@8 92
rlm@8 93 return addr;
rlm@8 94
rlm@8 95 endfunction
rlm@8 96
rlm@8 97 function CacheLineIndex getCacheLineIndex( InstReq req );
rlm@8 98 Bit#(AddrSz) addr = getAddr(req);
rlm@8 99 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
rlm@8 100 return index;
rlm@8 101 endfunction
rlm@8 102
rlm@8 103 function CacheLineTag getCacheLineTag( InstReq req );
rlm@8 104 Bit#(AddrSz) addr = getAddr(req);
rlm@8 105 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
rlm@8 106 return tag;
rlm@8 107 endfunction
rlm@8 108
rlm@8 109 function Bit#(AddrSz) getCacheLineAddr( InstReq req );
rlm@8 110 Bit#(AddrSz) addr = getAddr(req);
rlm@8 111 return ((addr >> 2) << 2);
rlm@8 112 endfunction
rlm@8 113
rlm@8 114 //----------------------------------------------------------------------
rlm@8 115 // Main module
rlm@8 116 //----------------------------------------------------------------------
rlm@8 117
rlm@8 118 (* doc = "synthesis attribute ram_style mkInstCache distributed;" *)
rlm@8 119 (* synthesize *)
rlm@8 120 module mkInstCache( ICache#(InstReq,InstResp) );
rlm@8 121
rlm@8 122 //-----------------------------------------------------------
rlm@8 123 // State
rlm@8 124
rlm@8 125 Reg#(CacheStage) stage <- mkReg(Init);
rlm@8 126
rlm@8 127 RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull();
rlm@8 128 RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull();
rlm@8 129
rlm@8 130 FIFO#(InstReq) reqQ <- mkFIFO();
rlm@8 131 FIFOF#(InstResp) respQ <- mkBFIFOF1();
rlm@8 132
rlm@8 133 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
rlm@8 134 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
rlm@8 135
rlm@8 136 Reg#(CacheLineIndex) initCounter <- mkReg(1);
rlm@8 137
rlm@8 138 // Statistics state
rlm@8 139
rlm@8 140 Reg#(Bool) statsEn <- mkReg(False);
rlm@8 141
rlm@8 142 Reg#(Stat) numAccesses <- mkReg(0);
rlm@8 143 Reg#(Stat) numMisses <- mkReg(0);
rlm@8 144 Reg#(Stat) numEvictions <- mkReg(0);
rlm@8 145
rlm@8 146 //-----------------------------------------------------------
rlm@8 147 // Name some wires
rlm@8 148
rlm@8 149 let req = reqQ.first();
rlm@8 150 let reqIndex = getCacheLineIndex(req);
rlm@8 151 let reqTag = getCacheLineTag(req);
rlm@8 152 let reqCacheLineAddr = getCacheLineAddr(req);
rlm@8 153 let refill = mainMemRespQ.first();
rlm@8 154
rlm@8 155 //-----------------------------------------------------------
rlm@8 156 // Initialize
rlm@8 157
rlm@8 158 rule init ( stage == Init );
rlm@8 159 traceTiny("mkInstCacheBlocking", "stage","i");
rlm@8 160 initCounter <= initCounter + 1;
rlm@8 161 cacheTagRam.upd(initCounter,Invalid);
rlm@8 162 if ( initCounter == 0 )
rlm@8 163 stage <= Access;
rlm@8 164 endrule
rlm@8 165
rlm@8 166 //-----------------------------------------------------------
rlm@8 167 // Cache access rule
rlm@8 168
rlm@8 169 rule access ( (stage == Access) && respQ.notFull() );
rlm@8 170
rlm@8 171 // Statistics
rlm@8 172
rlm@8 173 if ( statsEn )
rlm@8 174 numAccesses <= numAccesses + 1;
rlm@8 175
rlm@8 176 // Check tag and valid bit to see if this is a hit or a miss
rlm@8 177
rlm@8 178 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
rlm@8 179
rlm@8 180 // Handle cache hits ...
rlm@8 181
rlm@8 182 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
rlm@8 183 begin
rlm@8 184 traceTiny("mkInstCacheBlocking", "hitMiss","h");
rlm@8 185 reqQ.deq();
rlm@8 186
rlm@8 187 case ( req ) matches
rlm@8 188
rlm@8 189 tagged LoadReq .ld :
rlm@8 190 respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } );
rlm@8 191
rlm@8 192 tagged StoreReq .st :
rlm@8 193 $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" );
rlm@8 194
rlm@8 195 endcase
rlm@8 196
rlm@8 197 end
rlm@8 198
rlm@8 199 // Handle cache misses - since lines in instruction cache are
rlm@8 200 // never dirty we can always immediately issue a refill request
rlm@8 201
rlm@8 202 else
rlm@8 203 begin
rlm@8 204 traceTiny("mkInstCacheBlocking", "hitMiss","m");
rlm@8 205 if ( statsEn )
rlm@8 206 numMisses <= numMisses + 1;
rlm@8 207 if ( statsEn )
rlm@8 208 if ( isJust(cacheLineTag) )
rlm@8 209 numEvictions <= numEvictions + 1;
rlm@8 210
rlm@8 211 MainMemReq rfReq
rlm@8 212 = LoadReq { tag : 0,
rlm@8 213 addr : reqCacheLineAddr };
rlm@8 214
rlm@8 215 mainMemReqQ.enq(rfReq);
rlm@8 216 stage <= RefillResp;
rlm@8 217 end
rlm@8 218
rlm@8 219 endrule
rlm@8 220
rlm@8 221 //-----------------------------------------------------------
rlm@8 222 // Refill response rule
rlm@8 223
rlm@8 224 rule refillResp ( stage == RefillResp );
rlm@8 225 traceTiny("mkInstCacheBlocking", "stage","R");
rlm@8 226 traceTiny("mkInstCacheBlocking", "refill",refill);
rlm@8 227
rlm@8 228 // Write the new data into the cache and update the tag
rlm@8 229
rlm@8 230 mainMemRespQ.deq();
rlm@8 231 case ( mainMemRespQ.first() ) matches
rlm@8 232
rlm@8 233 tagged LoadResp .ld :
rlm@8 234 begin
rlm@8 235 cacheTagRam.upd(reqIndex,Valid(reqTag));
rlm@8 236 cacheDataRam.upd(reqIndex,ld.data);
rlm@8 237 end
rlm@8 238
rlm@8 239 tagged StoreResp .st :
rlm@8 240 noAction;
rlm@8 241
rlm@8 242 endcase
rlm@8 243
rlm@8 244 stage <= Access;
rlm@8 245 endrule
rlm@8 246
rlm@8 247 //-----------------------------------------------------------
rlm@8 248 // Methods
rlm@8 249
rlm@8 250 interface Client mmem_client;
rlm@8 251 interface Get request = fifoToGet(mainMemReqQ);
rlm@8 252 interface Put response = fifoToPut(mainMemRespQ);
rlm@8 253 endinterface
rlm@8 254
rlm@8 255 interface Server proc_server;
rlm@8 256 interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",toPut(reqQ));
rlm@8 257 interface Get response = traceGet("mkInstCacheBlocking", "respTiny",toGet(respQ));
rlm@8 258 endinterface
rlm@8 259
rlm@8 260 interface Put statsEn_put = toPut(asReg(statsEn));
rlm@8 261
rlm@8 262 interface ICacheStats stats;
rlm@8 263 interface Get num_accesses = toGet(asReg(numAccesses));
rlm@8 264 interface Get num_misses = toGet(asReg(numMisses));
rlm@8 265 interface Get num_evictions = toGet(asReg(numEvictions));
rlm@8 266 endinterface
rlm@8 267
rlm@8 268 endmodule
rlm@8 269