annotate modules/bluespec/Pygar/core/DataCacheBlocking.bsv @ 13:6d461680c6d9 pygar svn.14

[svn r14] more stuff
author punk
date Tue, 27 Apr 2010 09:03:28 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 // The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@8 23 import Connectable::*;
rlm@8 24 import GetPut::*;
rlm@8 25 import ClientServer::*;
rlm@8 26 import RegFile::*;
rlm@8 27 import FIFO::*;
rlm@8 28 import FIFOF::*;
rlm@8 29
rlm@8 30 import BFIFO::*;
rlm@8 31 import MemTypes::*;
rlm@8 32 import ProcTypes::*;
rlm@8 33 import Trace::*;
rlm@8 34
rlm@8 35 interface DCacheStats;
rlm@8 36 interface Get#(Stat) num_accesses;
rlm@8 37 interface Get#(Stat) num_misses;
rlm@8 38 interface Get#(Stat) num_writebacks;
rlm@8 39 endinterface
rlm@8 40
rlm@8 41 interface DCache#( type req_t, type resp_t );
rlm@8 42
rlm@8 43 // Interface from processor to cache
rlm@8 44 interface Server#(req_t,resp_t) proc_server;
rlm@8 45
rlm@8 46 // Interface from cache to main memory
rlm@8 47 interface Client#(MainMemReq,MainMemResp) mmem_client;
rlm@8 48
rlm@8 49 // Interface for enabling/disabling statistics
rlm@8 50 interface Put#(Bool) statsEn_put;
rlm@8 51
rlm@8 52 // Interface for collecting statistics
rlm@8 53 interface DCacheStats stats;
rlm@8 54
rlm@8 55 endinterface
rlm@8 56
rlm@8 57
rlm@8 58 //----------------------------------------------------------------------
rlm@8 59 // Cache Types
rlm@8 60 //----------------------------------------------------------------------
rlm@8 61
rlm@8 62 typedef 10 CacheLineIndexSz;
rlm@8 63 typedef 20 CacheLineTagSz;
rlm@8 64 typedef 32 CacheLineSz;
rlm@8 65
rlm@8 66 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
rlm@8 67 typedef Bit#(CacheLineTagSz) CacheLineTag;
rlm@8 68 typedef Bit#(CacheLineSz) CacheLine;
rlm@8 69
rlm@8 70 typedef enum
rlm@8 71 {
rlm@8 72 Init,
rlm@8 73 Access,
rlm@8 74 RefillReq,
rlm@8 75 RefillResp
rlm@8 76 }
rlm@8 77 CacheStage
rlm@8 78 deriving (Eq,Bits);
rlm@8 79
rlm@8 80 //----------------------------------------------------------------------
rlm@8 81 // Helper functions
rlm@8 82 //----------------------------------------------------------------------
rlm@8 83
rlm@8 84 function Bit#(AddrSz) getAddr( DataReq req );
rlm@8 85
rlm@8 86 Bit#(AddrSz) addr = ?;
rlm@8 87 case ( req ) matches
rlm@8 88 tagged LoadReq .ld : addr = ld.addr;
rlm@8 89 tagged StoreReq .st : addr = st.addr;
rlm@8 90 endcase
rlm@8 91
rlm@8 92 return addr;
rlm@8 93
rlm@8 94 endfunction
rlm@8 95
rlm@8 96 function CacheLineIndex getCacheLineIndex( DataReq req );
rlm@8 97 Bit#(AddrSz) addr = getAddr(req);
rlm@8 98 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
rlm@8 99 return index;
rlm@8 100 endfunction
rlm@8 101
rlm@8 102 function CacheLineTag getCacheLineTag( DataReq req );
rlm@8 103 Bit#(AddrSz) addr = getAddr(req);
rlm@8 104 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
rlm@8 105 return tag;
rlm@8 106 endfunction
rlm@8 107
rlm@8 108 function Bit#(AddrSz) getCacheLineAddr( DataReq req );
rlm@8 109 Bit#(AddrSz) addr = getAddr(req);
rlm@8 110 return ((addr >> 2) << 2);
rlm@8 111 endfunction
rlm@8 112
rlm@8 113 //----------------------------------------------------------------------
rlm@8 114 // Main module
rlm@8 115 //----------------------------------------------------------------------
rlm@8 116
rlm@8 117 (* doc = "synthesis attribute ram_style mkDataCache distributed;" *)
rlm@8 118 (* synthesize *)
rlm@8 119 module mkDataCache( DCache#(DataReq,DataResp) );
rlm@8 120
rlm@8 121 //-----------------------------------------------------------
rlm@8 122 // State
rlm@8 123
rlm@8 124 Reg#(CacheStage) stage <- mkReg(Init);
rlm@8 125
rlm@8 126 RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull();
rlm@8 127 RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull();
rlm@8 128
rlm@8 129 FIFO#(DataReq) reqQ <- mkFIFO();
rlm@8 130 FIFOF#(DataResp) respQ <- mkBFIFOF1();
rlm@8 131
rlm@8 132 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
rlm@8 133 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
rlm@8 134
rlm@8 135 Reg#(CacheLineIndex) initCounter <- mkReg(1);
rlm@8 136
rlm@8 137 // Statistics state
rlm@8 138
rlm@8 139 Reg#(Bool) statsEn <- mkReg(False);
rlm@8 140
rlm@8 141 Reg#(Stat) num_accesses <- mkReg(0);
rlm@8 142 Reg#(Stat) num_misses <- mkReg(0);
rlm@8 143 Reg#(Stat) num_writebacks <- mkReg(0);
rlm@8 144
rlm@8 145 //-----------------------------------------------------------
rlm@8 146 // Name some wires
rlm@8 147
rlm@8 148 let req = reqQ.first();
rlm@8 149 let reqIndex = getCacheLineIndex(req);
rlm@8 150 let reqTag = getCacheLineTag(req);
rlm@8 151 let reqCacheLineAddr = getCacheLineAddr(req);
rlm@8 152
rlm@8 153 //-----------------------------------------------------------
rlm@8 154 // Initialize
rlm@8 155
rlm@8 156 rule init ( stage == Init );
rlm@8 157 traceTiny("mkDataCacheBlocking", "stage","i");
rlm@8 158 initCounter <= initCounter + 1;
rlm@8 159 cacheTagRam.upd(initCounter,Invalid);
rlm@8 160 if ( initCounter == 0 )
rlm@8 161 stage <= Access;
rlm@8 162 endrule
rlm@8 163
rlm@8 164 //-----------------------------------------------------------
rlm@8 165 // Access cache rule
rlm@8 166
rlm@8 167 rule access ( (stage == Access) && respQ.notFull() );
rlm@8 168
rlm@8 169 // Statistics
rlm@8 170
rlm@8 171 if ( statsEn )
rlm@8 172 num_accesses <= num_accesses + 1;
rlm@8 173
rlm@8 174
rlm@8 175 // Get the corresponding tag from the rams
rlm@8 176
rlm@8 177 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
rlm@8 178
rlm@8 179 // Handle cache hits ...
rlm@8 180
rlm@8 181 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
rlm@8 182 begin
rlm@8 183 traceTiny("mkDataCacheBlocking", "hitMiss","h");
rlm@8 184 reqQ.deq();
rlm@8 185
rlm@8 186 case ( req ) matches
rlm@8 187
rlm@8 188 tagged LoadReq .ld :
rlm@8 189 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } );
rlm@8 190
rlm@8 191 tagged StoreReq .st :
rlm@8 192 begin
rlm@8 193 respQ.enq( StoreResp { tag : st.tag } );
rlm@8 194 cacheDataRam.upd(reqIndex,st.data);
rlm@8 195 end
rlm@8 196
rlm@8 197 endcase
rlm@8 198
rlm@8 199 end
rlm@8 200
rlm@8 201 // Handle cache misses ...
rlm@8 202
rlm@8 203 else
rlm@8 204 begin
rlm@8 205 traceTiny("mkDataCacheBlocking", "hitMiss","m");
rlm@8 206 if ( statsEn )
rlm@8 207 num_misses <= num_misses + 1;
rlm@8 208
rlm@8 209 // Currently we don't use dirty bits so we always writeback the data if it is valid
rlm@8 210
rlm@8 211 if ( isValid(cacheLineTag) )
rlm@8 212 begin
rlm@8 213
rlm@8 214 if ( statsEn )
rlm@8 215 num_writebacks <= num_writebacks + 1;
rlm@8 216
rlm@8 217 MainMemReq wbReq
rlm@8 218 = StoreReq { tag : 0,
rlm@8 219 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },
rlm@8 220 data : cacheDataRam.sub(reqIndex) };
rlm@8 221
rlm@8 222 mainMemReqQ.enq(wbReq);
rlm@8 223 stage <= RefillReq;
rlm@8 224 end
rlm@8 225
rlm@8 226 // Otherwise we can issue the refill request now
rlm@8 227
rlm@8 228 else
rlm@8 229 begin
rlm@8 230 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
rlm@8 231 stage <= RefillResp;
rlm@8 232 end
rlm@8 233
rlm@8 234 end
rlm@8 235
rlm@8 236 endrule
rlm@8 237
rlm@8 238 //-----------------------------------------------------------
rlm@8 239 // Refill request rule
rlm@8 240
rlm@8 241 rule refillReq ( stage == RefillReq );
rlm@8 242 traceTiny("mkDataCacheBlocking", "stage","r");
rlm@8 243 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
rlm@8 244 stage <= RefillResp;
rlm@8 245 endrule
rlm@8 246
rlm@8 247 //-----------------------------------------------------------
rlm@8 248 // Refill response rule
rlm@8 249
rlm@8 250 rule refillResp ( stage == RefillResp );
rlm@8 251 traceTiny("mkDataCacheBlocking", "stage","R");
rlm@8 252 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first());
rlm@8 253
rlm@8 254 // Write the new data into the cache and update the tag
rlm@8 255
rlm@8 256 mainMemRespQ.deq();
rlm@8 257 case ( mainMemRespQ.first() ) matches
rlm@8 258
rlm@8 259 tagged LoadResp .ld :
rlm@8 260 begin
rlm@8 261 cacheTagRam.upd(reqIndex,Valid(reqTag));
rlm@8 262 cacheDataRam.upd(reqIndex,ld.data);
rlm@8 263 end
rlm@8 264
rlm@8 265 tagged StoreResp .st :
rlm@8 266 noAction;
rlm@8 267
rlm@8 268 endcase
rlm@8 269
rlm@8 270 stage <= Access;
rlm@8 271 endrule
rlm@8 272
rlm@8 273 //-----------------------------------------------------------
rlm@8 274 // Methods
rlm@8 275
rlm@8 276 interface Client mmem_client;
rlm@8 277 interface Get request = toGet(mainMemReqQ);
rlm@8 278 interface Put response = toPut(mainMemRespQ);
rlm@8 279 endinterface
rlm@8 280
rlm@8 281 interface Server proc_server;
rlm@8 282 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",toPut(reqQ));
rlm@8 283 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",toGet(respQ));
rlm@8 284 endinterface
rlm@8 285
rlm@8 286 interface Put statsEn_put = toPut(asReg(statsEn));
rlm@8 287
rlm@8 288 interface DCacheStats stats;
rlm@8 289 interface Get num_accesses = toGet(asReg(num_accesses));
rlm@8 290 interface Get num_misses = toGet(asReg(num_misses));
rlm@8 291 interface Get num_writebacks = toGet(asReg(num_writebacks));
rlm@8 292 endinterface
rlm@8 293
rlm@8 294 endmodule
rlm@8 295