pygar: modules/bluespec/Pygar/core/Processor.bsv annotate

annotate modules/bluespec/Pygar/core/Processor.bsv @ 9:a66d70a89c85 pygar svn.10

[svn r10] added week 3 progress report. Please tell me what you think!

author	rlm
date	Fri, 23 Apr 2010 06:08:21 -0400
parents	74716e9a81cc
children	50af57801d6e

rev	line source
rlm@8	1 /// The MIT License
rlm@8	2
rlm@8	3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8	4
rlm@8	5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8	6 // of this software and associated documentation files (the "Software"), to deal
rlm@8	7 // in the Software without restriction, including without limitation the rights
rlm@8	8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8	9 // copies of the Software, and to permit persons to whom the Software is
rlm@8	10 // furnished to do so, subject to the following conditions:
rlm@8	11
rlm@8	12 // The above copyright notice and this permission notice shall be included in
rlm@8	13 // all copies or substantial portions of the Software.
rlm@8	14
rlm@8	15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8	16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8	17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8	18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8	19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8	20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8	21 // THE SOFTWARE.
rlm@8	22
rlm@8	23 import Connectable::*;
rlm@8	24 import GetPut::*;
rlm@8	25 import ClientServer::*;
rlm@8	26 import RegFile::*;
rlm@8	27
rlm@8	28 import FIFO::*;
rlm@8	29 import FIFOF::*;
rlm@8	30 import SFIFO::*;
rlm@8	31 import RWire::*;
rlm@8	32
rlm@8	33 import BFIFO::*;
rlm@8	34 import MemTypes::*;
rlm@8	35 import ProcTypes::*;
rlm@8	36 import BRegFile::*;
rlm@8	37 import BranchPred::*;
rlm@8	38 //import PathTypes::*; This is only there to force the debugging
rlm@8	39
rlm@8	40 import Trace::*;
rlm@8	41
rlm@8	42 //AWB includes
rlm@8	43 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8	44 `include "asim/provides/soft_connections.bsh"
rlm@8	45 `include "asim/provides/common_services.bsh"
rlm@8	46
rlm@8	47 // Local includes
rlm@8	48 `include "asim/provides/processor_library.bsh"
rlm@8	49 `include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh"
rlm@8	50 `include "asim/provides/common_services.bsh"
rlm@8	51 `include "asim/dict/STATS_PROCESSOR.bsh"
rlm@8	52
rlm@8	53 interface ProcStats;
rlm@8	54 interface Get#(Stat) num_cycles;
rlm@8	55 interface Get#(Stat) num_inst;
rlm@8	56 endinterface
rlm@8	57
rlm@8	58 interface CPUToHost;
rlm@8	59 method Bit#(32) cpuToHost(int req);
rlm@8	60 endinterface
rlm@8	61
rlm@8	62 interface Proc;
rlm@8	63
rlm@8	64 // Interface from processor to caches
rlm@8	65 interface Client#(DataReq,DataResp) dmem_client;
rlm@8	66 interface Client#(InstReq,InstResp) imem_client;
rlm@8	67
rlm@8	68 // Interface for enabling/disabling statistics on the rest of the core
rlm@8	69 interface Get#(Bool) statsEn_get;
rlm@8	70
rlm@8	71 // Interface for collecting statistics.
rlm@8	72 interface ProcStats stats;
rlm@8	73
rlm@8	74 // Interface to host
rlm@8	75 interface CPUToHost tohost;
rlm@8	76
rlm@8	77 endinterface
rlm@8	78
rlm@8	79
rlm@8	80 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
rlm@8	81
rlm@8	82 //-----------------------------------------------------------
rlm@8	83 // Register file module
rlm@8	84 //-----------------------------------------------------------
rlm@8	85
rlm@8	86 interface BRFile;
rlm@8	87 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	88 method Bit#(32) rd1( Rindx rindx );
rlm@8	89 method Bit#(32) rd2( Rindx rindx );
rlm@8	90 endinterface
rlm@8	91
rlm@8	92 module mkBRFile( BRFile );
rlm@8	93
rlm@8	94 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
rlm@8	95
rlm@8	96 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	97 rfile.upd( rindx, data );
rlm@8	98 endmethod
rlm@8	99
rlm@8	100 method Bit#(32) rd1( Rindx rindx );
rlm@8	101 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	102 endmethod
rlm@8	103
rlm@8	104 method Bit#(32) rd2( Rindx rindx );
rlm@8	105 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	106 endmethod
rlm@8	107
rlm@8	108 endmodule
rlm@8	109
rlm@8	110 //-----------------------------------------------------------
rlm@8	111 // Helper functions
rlm@8	112 //-----------------------------------------------------------
rlm@8	113
rlm@8	114 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
rlm@8	115 return zeroExtend( pack( signedLT(val1,val2) ) );
rlm@8	116 endfunction
rlm@8	117
rlm@8	118 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
rlm@8	119 return zeroExtend( pack( val1 < val2 ) );
rlm@8	120 endfunction
rlm@8	121
rlm@8	122 function Bit#(32) rshft( Bit#(32) val );
rlm@8	123 return zeroExtend(val[4:0]);
rlm@8	124 endfunction
rlm@8	125
rlm@8	126
rlm@8	127 //-----------------------------------------------------------
rlm@8	128 // Find funct for wbQ
rlm@8	129 //-----------------------------------------------------------
rlm@8	130 function Bool findwbf(Rindx fVal, WBResult cmpVal);
rlm@8	131 case (cmpVal) matches
rlm@8	132 tagged WB_ALU {data:.res, dest:.rd} :
rlm@8	133 return (fVal == rd);
rlm@8	134 tagged WB_Load .rd :
rlm@8	135 return (fVal == rd);
rlm@8	136 tagged WB_Store .st :
rlm@8	137 return False;
rlm@8	138 tagged WB_Host .x :
rlm@8	139 return False;
rlm@8	140 endcase
rlm@8	141 endfunction
rlm@8	142
rlm@8	143
rlm@8	144 //-----------------------------------------------------------
rlm@8	145 // Stall funct for wbQ
rlm@8	146 //-----------------------------------------------------------
rlm@8	147 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
rlm@8	148 case (inst) matches
rlm@8	149 // -- Memory Ops ------------------------------------------------
rlm@8	150 tagged LW .it :
rlm@8	151 return f.find(it.rbase);
rlm@8	152 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
rlm@8	153 return (f.find(addr) \|\| f.find2(dreg));
rlm@8	154
rlm@8	155 // -- Simple Ops ------------------------------------------------
rlm@8	156 tagged ADDIU .it : return f.find(it.rsrc);
rlm@8	157 tagged SLTI .it : return f.find(it.rsrc);
rlm@8	158 tagged SLTIU .it : return f.find(it.rsrc);
rlm@8	159 tagged ANDI .it : return f.find(it.rsrc);
rlm@8	160 tagged ORI .it : return f.find(it.rsrc);
rlm@8	161 tagged XORI .it : return f.find(it.rsrc);
rlm@8	162
rlm@8	163 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
rlm@8	164 tagged SLL .it : return f.find(it.rsrc);
rlm@8	165 tagged SRL .it : return f.find(it.rsrc);
rlm@8	166 tagged SRA .it : return f.find(it.rsrc);
rlm@8	167 tagged SLLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	168 tagged SRLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	169 tagged SRAV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	170 tagged ADDU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	171 tagged SUBU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	172 tagged AND .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	173 tagged OR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	174 tagged XOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	175 tagged NOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	176 tagged SLT .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	177 tagged SLTU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	178
rlm@8	179
rlm@8	180 // -- Branches --------------------------------------------------
rlm@8	181
rlm@8	182 tagged BLEZ .it : return (f.find(it.rsrc));
rlm@8	183 tagged BGTZ .it : return (f.find(it.rsrc));
rlm@8	184 tagged BLTZ .it : return (f.find(it.rsrc));
rlm@8	185 tagged BGEZ .it : return (f.find(it.rsrc));
rlm@8	186 tagged BEQ .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	187 tagged BNE .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	188
rlm@8	189 // -- Jumps -----------------------------------------------------
rlm@8	190
rlm@8	191 tagged J .it : return False;
rlm@8	192 tagged JR .it : return f.find(it.rsrc);
rlm@8	193 tagged JALR .it : return f.find(it.rsrc);
rlm@8	194 tagged JAL .it : return False;
rlm@8	195
rlm@8	196 // -- Cop0 ------------------------------------------------------
rlm@8	197
rlm@8	198 tagged MTC0 .it : return f.find(it.rsrc);
rlm@8	199 tagged MFC0 .it : return False;
rlm@8	200
rlm@8	201 // -- Illegal ---------------------------------------------------
rlm@8	202
rlm@8	203 default : return False;
rlm@8	204
rlm@8	205 endcase
rlm@8	206 endfunction
rlm@8	207 //-----------------------------------------------------------
rlm@8	208 // Reference processor
rlm@8	209 //-----------------------------------------------------------
rlm@8	210
rlm@8	211
rlm@8	212 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
rlm@8	213 //(* synthesize *)
rlm@8	214
rlm@8	215 module [CONNECTED_MODULE] mkProc( Proc );
rlm@8	216
rlm@8	217 //-----------------------------------------------------------
rlm@8	218 // Debug port
rlm@8	219
rlm@8	220 ServerStub_PROCESSORSYSTEMRRR server_stub <- mkServerStub_PROCESSORSYSTEMRRR();
rlm@8	221
rlm@8	222
rlm@8	223 //-----------------------------------------------------------
rlm@8	224 // State
rlm@8	225
rlm@8	226 // Standard processor state
rlm@8	227
rlm@8	228 Reg#(Addr) pc <- mkReg(32'h00001000);
rlm@8	229 Reg#(Epoch) epoch <- mkReg(0);
rlm@8	230 Reg#(Stage) stage <- mkReg(PCgen);
rlm@8	231 BRFile rf <- mkBRFile;
rlm@8	232
rlm@8	233 // Branch Prediction
rlm@8	234 BranchPred bp <- mkBranchPred();
rlm@8	235 FIFO#(PCStat) execpc <- mkLFIFO();
rlm@8	236
rlm@8	237 // Pipelines
rlm@8	238 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
rlm@8	239 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
rlm@8	240
rlm@8	241 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
rlm@8	242 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
rlm@8	243 Reg#(Bool) cp0_statsEn <- mkReg(False);
rlm@8	244
rlm@8	245 // Memory request/response state
rlm@8	246
rlm@8	247 FIFO#(InstReq) instReqQ <- mkBFIFO1();
rlm@8	248 FIFO#(InstResp) instRespQ <- mkFIFO();
rlm@8	249
rlm@8	250 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
rlm@8	251 FIFO#(DataResp) dataRespQ <- mkFIFO();
rlm@8	252
rlm@8	253 // Statistics state
rlm@8	254 Reg#(Stat) num_cycles <- mkReg(0);
rlm@8	255 Reg#(Stat) num_inst <- mkReg(0);
rlm@8	256
rlm@8	257 //Or:
rlm@8	258 // Statistics state
rlm@8	259 //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
rlm@8	260 //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
rlm@8	261
rlm@8	262 //-----------------------------------------------------------
rlm@8	263 // Rules
rlm@8	264
rlm@8	265 (* descending_urgency = "exec, pcgen" *)
rlm@8	266 rule pcgen; //( stage == PCgen );
rlm@8	267 let pc_plus4 = pc + 4;
rlm@8	268
rlm@8	269 traceTiny("mkProc", "pc",pc);
rlm@8	270 traceTiny("mkProc", "pcgen","P");
rlm@8	271 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
rlm@8	272
rlm@8	273 let next_pc = bp.get(pc);
rlm@8	274 if (next_pc matches tagged Valid .npc)
rlm@8	275 begin
rlm@8	276 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
rlm@8	277 pc <= npc;
rlm@8	278 end
rlm@8	279 else
rlm@8	280 begin
rlm@8	281 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
rlm@8	282 pc <= pc_plus4;
rlm@8	283 end
rlm@8	284
rlm@8	285 endrule
rlm@8	286
rlm@8	287 rule discard (instRespQ.first() matches tagged LoadResp .ld
rlm@8	288 &&& ld.tag != epoch);
rlm@8	289 traceTiny("mkProc", "stage", "D");
rlm@8	290 instRespQ.deq();
rlm@8	291 endrule
rlm@8	292
rlm@8	293 (* conflict_free = "exec, writeback" *)
rlm@8	294 rule exec (instRespQ.first() matches tagged LoadResp.ld
rlm@8	295 &&& (ld.tag == epoch)
rlm@8	296 &&& unpack(ld.data) matches .inst
rlm@8	297 &&& !stall(inst, wbQ));
rlm@8	298
rlm@8	299 // Some abbreviations
rlm@8	300 let sext = signExtend;
rlm@8	301 let zext = zeroExtend;
rlm@8	302 let sra = signedShiftRight;
rlm@8	303
rlm@8	304 // Get the instruction
rlm@8	305
rlm@8	306 instRespQ.deq();
rlm@8	307 Instr inst
rlm@8	308 = case ( instRespQ.first() ) matches
rlm@8	309 tagged LoadResp .ld : return unpack(ld.data);
rlm@8	310 tagged StoreResp .st : return ?;
rlm@8	311 endcase;
rlm@8	312
rlm@8	313 // Get the PC info
rlm@8	314 let instrpc = pcQ.first().qpc;
rlm@8	315 let pc_plus4 = instrpc + 4;
rlm@8	316
rlm@8	317 Bool branchTaken = False;
rlm@8	318 Addr newPC = pc_plus4;
rlm@8	319
rlm@8	320 // Tracing
rlm@8	321 traceTiny("mkProc", "exec","X");
rlm@8	322 traceTiny("mkProc", "exInstTiny",inst);
rlm@8	323 traceFull("mkProc", "exInstFull",inst);
rlm@8	324
rlm@8	325 case ( inst ) matches
rlm@8	326
rlm@8	327 // -- Memory Ops ------------------------------------------------
rlm@8	328
rlm@8	329 tagged LW .it :
rlm@8	330 begin
rlm@8	331 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	332 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
rlm@8	333 wbQ.enq(tagged WB_Load it.rdst);
rlm@8	334 end
rlm@8	335
rlm@8	336 tagged SW .it :
rlm@8	337 begin
rlm@8	338 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	339 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
rlm@8	340 wbQ.enq(tagged WB_Store);
rlm@8	341 end
rlm@8	342
rlm@8	343 // -- Simple Ops ------------------------------------------------
rlm@8	344
rlm@8	345 tagged ADDIU .it :
rlm@8	346 begin
rlm@8	347 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
rlm@8	348 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
rlm@8	349 end
rlm@8	350 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
rlm@8	351 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
rlm@8	352 tagged ANDI .it :
rlm@8	353 begin
rlm@8	354 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	355 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
rlm@8	356 end
rlm@8	357 tagged ORI .it :
rlm@8	358 begin
rlm@8	359 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	360 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) \| zext_it_imm)} );
rlm@8	361 end
rlm@8	362 tagged XORI .it :
rlm@8	363 begin
rlm@8	364 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	365 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
rlm@8	366 end
rlm@8	367 tagged LUI .it :
rlm@8	368 begin
rlm@8	369 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	370 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
rlm@8	371 end
rlm@8	372
rlm@8	373 tagged SLL .it :
rlm@8	374 begin
rlm@8	375 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	376 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
rlm@8	377 end
rlm@8	378 tagged SRL .it :
rlm@8	379 begin
rlm@8	380 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	381 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
rlm@8	382 end
rlm@8	383 tagged SRA .it :
rlm@8	384 begin
rlm@8	385 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	386 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
rlm@8	387 end
rlm@8	388 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
rlm@8	389 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
rlm@8	390 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
rlm@8	391 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
rlm@8	392 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
rlm@8	393 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
rlm@8	394 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2) )} );
rlm@8	395 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
rlm@8	396 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2)) )} );
rlm@8	397 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	398 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	399
rlm@8	400 // -- Branches --------------------------------------------------
rlm@8	401
rlm@8	402 tagged BLEZ .it :
rlm@8	403 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
rlm@8	404 begin
rlm@8	405 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	406 branchTaken = True;
rlm@8	407 end
rlm@8	408
rlm@8	409 tagged BGTZ .it :
rlm@8	410 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
rlm@8	411 begin
rlm@8	412 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	413 branchTaken = True;
rlm@8	414 end
rlm@8	415
rlm@8	416 tagged BLTZ .it :
rlm@8	417 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
rlm@8	418 begin
rlm@8	419 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	420 branchTaken = True;
rlm@8	421 end
rlm@8	422
rlm@8	423 tagged BGEZ .it :
rlm@8	424 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
rlm@8	425 begin
rlm@8	426 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	427 branchTaken = True;
rlm@8	428 end
rlm@8	429
rlm@8	430 tagged BEQ .it :
rlm@8	431 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
rlm@8	432 begin
rlm@8	433 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	434 branchTaken = True;
rlm@8	435 end
rlm@8	436
rlm@8	437 tagged BNE .it :
rlm@8	438 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
rlm@8	439 begin
rlm@8	440 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	441 branchTaken = True;
rlm@8	442 end
rlm@8	443
rlm@8	444 // -- Jumps -----------------------------------------------------
rlm@8	445
rlm@8	446 tagged J .it :
rlm@8	447 begin
rlm@8	448 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	449 branchTaken = True;
rlm@8	450 end
rlm@8	451
rlm@8	452 tagged JR .it :
rlm@8	453 begin
rlm@8	454 newPC = rf.rd1(it.rsrc);
rlm@8	455 branchTaken = True;
rlm@8	456 end
rlm@8	457
rlm@8	458 tagged JAL .it :
rlm@8	459 begin
rlm@8	460 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
rlm@8	461 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	462 branchTaken = True;
rlm@8	463 end
rlm@8	464
rlm@8	465 tagged JALR .it :
rlm@8	466 begin
rlm@8	467 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
rlm@8	468 newPC = rf.rd1(it.rsrc);
rlm@8	469 branchTaken = True;
rlm@8	470 end
rlm@8	471
rlm@8	472 // -- Cop0 ------------------------------------------------------
rlm@8	473
rlm@8	474 tagged MTC0 .it :
rlm@8	475 begin
rlm@8	476 case ( it.cop0dst )
rlm@8	477 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
rlm@8	478 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
rlm@8	479 default :
rlm@8	480 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
rlm@8	481 endcase
rlm@8	482 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
rlm@8	483 end
rlm@8	484
rlm@8	485 //this is host stuff?
rlm@8	486 tagged MFC0 .it :
rlm@8	487 begin
rlm@8	488 case ( it.cop0src )
rlm@8	489 // not actually an ALU instruction but don't have the format otherwise
rlm@8	490 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
rlm@8	491 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
rlm@8	492 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
rlm@8	493 default :
rlm@8	494 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
rlm@8	495 endcase
rlm@8	496 end
rlm@8	497
rlm@8	498 // -- Illegal ---------------------------------------------------
rlm@8	499
rlm@8	500 default :
rlm@8	501 $display( " RTL-ERROR : %m : Illegal instruction !" );
rlm@8	502
rlm@8	503 endcase
rlm@8	504
rlm@8	505 //evaluate branch prediction
rlm@8	506 Addr ppc = pcQ.first().qnxtpc; //predicted branch
rlm@8	507 if (ppc != newPC) //prediction wrong
rlm@8	508 begin
rlm@8	509 epoch <= pcQ.first().qepoch + 1;
rlm@8	510 bp.upd(instrpc, newPC); //update branch predictor
rlm@8	511 pcQ.clear();
rlm@8	512 pc <= newPC;
rlm@8	513 end
rlm@8	514 else
rlm@8	515 pcQ.deq();
rlm@8	516
rlm@8	517 if ( cp0_statsEn )
rlm@8	518 num_inst <= num_inst+1;
rlm@8	519
rlm@8	520 endrule
rlm@8	521
rlm@8	522 rule writeback; // ( stage == Writeback );
rlm@8	523 traceTiny("mkProc", "writeback","W");
rlm@8	524
rlm@8	525
rlm@8	526 // get what to do off the writeback queue
rlm@8	527 wbQ.deq();
rlm@8	528 case (wbQ.first()) matches
rlm@8	529 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
rlm@8	530 tagged WB_Load .regWr :
rlm@8	531 begin
rlm@8	532 dataRespQ.deq();
rlm@8	533 if (dataRespQ.first() matches tagged LoadResp .ld)
rlm@8	534 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
rlm@8	535 end
rlm@8	536 tagged WB_Store : dataRespQ.deq();
rlm@8	537 tagged WB_Host .dat : noAction;
rlm@8	538 endcase
rlm@8	539
rlm@8	540 endrule
rlm@8	541
rlm@8	542 rule inc_num_cycles;
rlm@8	543 if ( cp0_statsEn )
rlm@8	544 num_cycles <= num_cycles+1;
rlm@8	545 endrule
rlm@8	546 // THis rule breaks things
rlm@8	547 // rule handleCPUToHost;
rlm@8	548 // let req <- server_stub.acceptRequest_ReadCPUToHost();
rlm@8	549 // case (req)
rlm@8	550 // 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
rlm@8	551 // 1: server_stub.sendResponse_ReadCPUToHost(pc);
rlm@8	552 // 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
rlm@8	553 // endcase
rlm@8	554 // endrule
rlm@8	555 //-----------------------------------------------------------
rlm@8	556 // My Adds
rlm@8	557 //-----------------------------------------------------------
rlm@8	558
rlm@8	559 //-----------------------------------------------------------
rlm@8	560 // Methods
rlm@8	561
rlm@8	562 interface Client imem_client;
rlm@8	563 interface Get request = toGet(instReqQ);
rlm@8	564 interface Put response = toPut(instRespQ);
rlm@8	565 endinterface
rlm@8	566
rlm@8	567 interface Client dmem_client;
rlm@8	568 interface Get request = toGet(dataReqQ);
rlm@8	569 interface Put response = toPut(dataRespQ);
rlm@8	570 endinterface
rlm@8	571
rlm@8	572 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
rlm@8	573
rlm@8	574 interface ProcStats stats;
rlm@8	575 interface Get num_cycles = toGet(asReg(num_cycles));
rlm@8	576 interface Get num_inst = toGet(asReg(num_inst));
rlm@8	577 endinterface
rlm@8	578
rlm@8	579 interface CPUToHost tohost;
rlm@8	580 method Bit#(32) cpuToHost(int req);
rlm@8	581 return (case (req)
rlm@8	582 0: cp0_tohost;
rlm@8	583 1: pc;
rlm@8	584 2: zeroExtend(pack(stage));
rlm@8	585 endcase);
rlm@8	586 endmethod
rlm@8	587 endinterface
rlm@8	588
rlm@8	589 endmodule
rlm@8	590

Mercurial > pygar

annotate modules/bluespec/Pygar/core/Processor.bsv @ 9:a66d70a89c85 pygar svn.10