annotate modules/bluespec/Pygar/core/BRegFile.bsv @ 9:a66d70a89c85 pygar svn.10

[svn r10] added week 3 progress report. Please tell me what you think!
author rlm
date Fri, 23 Apr 2010 06:08:21 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 import RegFile::*;
rlm@8 2 import RWire::*;
rlm@8 3 import ProcTypes::*;
rlm@8 4
rlm@8 5 //-----------------------------------------------------------
rlm@8 6 // Register file module
rlm@8 7 //-----------------------------------------------------------
rlm@8 8
rlm@8 9 interface BRegFile #(type index_t, type data_t);
rlm@8 10 method Action upd(index_t addr, data_t data);
rlm@8 11 method data_t sub(index_t addr);
rlm@8 12 endinterface
rlm@8 13
rlm@8 14 module mkBRegFile(RegFile#(index_t, data_t))
rlm@8 15 provisos (Bits#(index_t, size_index),
rlm@8 16 Bits#(data_t, size_data),
rlm@8 17 Eq#(index_t),
rlm@8 18 Bounded#(index_t) );
rlm@8 19
rlm@8 20 RegFile#(index_t, data_t) rf <- mkRegFileWCF(minBound, maxBound);
rlm@8 21 RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();
rlm@8 22
rlm@8 23 method Action upd (index_t r, data_t d);
rlm@8 24 rf.upd(r,d);
rlm@8 25 rw.wset(tuple2(r,d));
rlm@8 26 endmethod
rlm@8 27
rlm@8 28 method data_t sub (index_t r);
rlm@8 29 case (rw.wget()) matches
rlm@8 30 tagged Valid {.wr, .d} :
rlm@8 31 return (wr == r) ? d : rf.sub(r);
rlm@8 32 tagged Invalid : return rf.sub(r);
rlm@8 33 endcase
rlm@8 34 endmethod
rlm@8 35
rlm@8 36 endmodule