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1 // The MIT License
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2
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3 // Copyright (c) 2009 Massachusetts Institute of Technology
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4
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5 // Permission is hereby granted, free of charge, to any person obtaining a copy
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6 // of this software and associated documentation files (the "Software"), to deal
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7 // in the Software without restriction, including without limitation the rights
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8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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9 // copies of the Software, and to permit persons to whom the Software is
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10 // furnished to do so, subject to the following conditions:
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11
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12 // The above copyright notice and this permission notice shall be included in
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13 // all copies or substantial portions of the Software.
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14
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15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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21 // THE SOFTWARE.
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22
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23 import Connectable::*;
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24 import GetPut::*;
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25 import ClientServer::*;
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26 import RegFile::*;
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27 import FIFO::*;
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28 import FIFOF::*;
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29
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30 import BFIFO::*;
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31 import MemTypes::*;
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32 import ProcTypes::*;
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33 import Trace::*;
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34
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35 interface DCacheStats;
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36 interface Get#(Stat) num_accesses;
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37 interface Get#(Stat) num_misses;
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38 interface Get#(Stat) num_writebacks;
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39 endinterface
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40
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41 interface DCache#( type req_t, type resp_t );
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42
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43 // Interface from processor to cache
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44 interface Server#(req_t,resp_t) proc_server;
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45
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46 // Interface from cache to main memory
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47 interface Client#(MainMemReq,MainMemResp) mmem_client;
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48
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49 // Interface for enabling/disabling statistics
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50 interface Put#(Bool) statsEn_put;
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51
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52 // Interface for collecting statistics
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53 interface DCacheStats stats;
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54
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55 endinterface
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56
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57
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58 //----------------------------------------------------------------------
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59 // Cache Types
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60 //----------------------------------------------------------------------
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61
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62 typedef 10 CacheLineIndexSz;
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63 typedef 20 CacheLineTagSz;
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64 typedef 32 CacheLineSz;
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65
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66 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
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67 typedef Bit#(CacheLineTagSz) CacheLineTag;
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68 typedef Bit#(CacheLineSz) CacheLine;
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69
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70 typedef enum
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71 {
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72 Init,
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73 Access,
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74 RefillReq,
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75 RefillResp
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76 }
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77 CacheStage
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78 deriving (Eq,Bits);
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79
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80 //----------------------------------------------------------------------
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81 // Helper functions
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82 //----------------------------------------------------------------------
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83
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84 function Bit#(AddrSz) getAddr( DataReq req );
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85
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86 Bit#(AddrSz) addr = ?;
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87 case ( req ) matches
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88 tagged LoadReq .ld : addr = ld.addr;
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89 tagged StoreReq .st : addr = st.addr;
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90 endcase
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91
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92 return addr;
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93
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94 endfunction
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95
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96 function CacheLineIndex getCacheLineIndex( DataReq req );
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97 Bit#(AddrSz) addr = getAddr(req);
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98 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
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99 return index;
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100 endfunction
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101
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102 function CacheLineTag getCacheLineTag( DataReq req );
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103 Bit#(AddrSz) addr = getAddr(req);
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104 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
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105 return tag;
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106 endfunction
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107
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108 function Bit#(AddrSz) getCacheLineAddr( DataReq req );
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109 Bit#(AddrSz) addr = getAddr(req);
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110 return ((addr >> 2) << 2);
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111 endfunction
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112
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113 //----------------------------------------------------------------------
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114 // Main module
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115 //----------------------------------------------------------------------
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116
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117 (* doc = "synthesis attribute ram_style mkDataCache distributed;" *)
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118 (* synthesize *)
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119 module mkDataCache( DCache#(DataReq,DataResp) );
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120
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121 //-----------------------------------------------------------
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122 // State
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123
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124 Reg#(CacheStage) stage <- mkReg(Init);
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125
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126 RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull();
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127 RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull();
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128
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129 FIFO#(DataReq) reqQ <- mkFIFO();
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130 FIFOF#(DataResp) respQ <- mkBFIFOF1();
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131
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132 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
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133 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
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134
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135 Reg#(CacheLineIndex) initCounter <- mkReg(1);
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136
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137 // Statistics state
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138
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139 Reg#(Bool) statsEn <- mkReg(False);
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140
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141 Reg#(Stat) num_accesses <- mkReg(0);
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142 Reg#(Stat) num_misses <- mkReg(0);
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143 Reg#(Stat) num_writebacks <- mkReg(0);
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144
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145 //-----------------------------------------------------------
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146 // Name some wires
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147
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148 let req = reqQ.first();
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149 let reqIndex = getCacheLineIndex(req);
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150 let reqTag = getCacheLineTag(req);
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151 let reqCacheLineAddr = getCacheLineAddr(req);
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152
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153 //-----------------------------------------------------------
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154 // Initialize
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155
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156 rule init ( stage == Init );
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157 traceTiny("mkDataCacheBlocking", "stage","i");
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158 initCounter <= initCounter + 1;
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159 cacheTagRam.upd(initCounter,Invalid);
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160 if ( initCounter == 0 )
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161 stage <= Access;
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162 endrule
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163
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164 //-----------------------------------------------------------
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165 // Access cache rule
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166
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167 rule access ( (stage == Access) && respQ.notFull() );
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168
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169 // Statistics
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170
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171 if ( statsEn )
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172 num_accesses <= num_accesses + 1;
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173
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174
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175 // Get the corresponding tag from the rams
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176
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177 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
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178
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179 // Handle cache hits ...
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180
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181 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
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182 begin
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183 traceTiny("mkDataCacheBlocking", "hitMiss","h");
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184 reqQ.deq();
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185
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186 case ( req ) matches
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187
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188 tagged LoadReq .ld :
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189 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } );
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190
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191 tagged StoreReq .st :
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192 begin
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193 respQ.enq( StoreResp { tag : st.tag } );
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194 cacheDataRam.upd(reqIndex,st.data);
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195 end
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196
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197 endcase
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198
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199 end
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200
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201 // Handle cache misses ...
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202
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203 else
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204 begin
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205 traceTiny("mkDataCacheBlocking", "hitMiss","m");
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206 if ( statsEn )
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207 num_misses <= num_misses + 1;
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208
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209 // Currently we don't use dirty bits so we always writeback the data if it is valid
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210
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211 if ( isValid(cacheLineTag) )
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212 begin
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213
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214 if ( statsEn )
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215 num_writebacks <= num_writebacks + 1;
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216
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217 MainMemReq wbReq
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218 = StoreReq { tag : 0,
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219 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },
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220 data : cacheDataRam.sub(reqIndex) };
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221
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222 mainMemReqQ.enq(wbReq);
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223 stage <= RefillReq;
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224 end
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225
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226 // Otherwise we can issue the refill request now
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227
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228 else
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229 begin
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230 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
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231 stage <= RefillResp;
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232 end
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233
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234 end
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235
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236 endrule
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237
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238 //-----------------------------------------------------------
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239 // Refill request rule
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240
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241 rule refillReq ( stage == RefillReq );
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242 traceTiny("mkDataCacheBlocking", "stage","r");
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243 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
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244 stage <= RefillResp;
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245 endrule
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246
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247 //-----------------------------------------------------------
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248 // Refill response rule
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249
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250 rule refillResp ( stage == RefillResp );
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251 traceTiny("mkDataCacheBlocking", "stage","R");
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252 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first());
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253
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254 // Write the new data into the cache and update the tag
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255
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256 mainMemRespQ.deq();
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257 case ( mainMemRespQ.first() ) matches
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258
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259 tagged LoadResp .ld :
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260 begin
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261 cacheTagRam.upd(reqIndex,Valid(reqTag));
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262 cacheDataRam.upd(reqIndex,ld.data);
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263 end
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264
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265 tagged StoreResp .st :
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266 noAction;
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267
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268 endcase
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269
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270 stage <= Access;
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271 endrule
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272
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273 //-----------------------------------------------------------
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274 // Methods
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275
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276 interface Client mmem_client;
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277 interface Get request = toGet(mainMemReqQ);
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278 interface Put response = toPut(mainMemRespQ);
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279 endinterface
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280
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281 interface Server proc_server;
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282 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",toPut(reqQ));
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283 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",toGet(respQ));
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284 endinterface
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285
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286 interface Put statsEn_put = toPut(asReg(statsEn));
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287
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288 interface DCacheStats stats;
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289 interface Get num_accesses = toGet(asReg(num_accesses));
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290 interface Get num_misses = toGet(asReg(num_misses));
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291 interface Get num_writebacks = toGet(asReg(num_writebacks));
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292 endinterface
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293
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294 endmodule
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295
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