annotate modules/bluespec/Pygar/lab4/Core.bsv @ 15:a1833d9f6e3d pygar svn.16

[svn r16] Recent
author punk
date Tue, 27 Apr 2010 13:11:45 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 // The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@8 23 import Connectable::*;
rlm@8 24 import GetPut::*;
rlm@8 25 import ClientServer::*;
rlm@8 26
rlm@8 27 //AWB includes
rlm@8 28 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8 29 `include "asim/provides/soft_connections.bsh"
rlm@8 30 `include "asim/provides/common_services.bsh"
rlm@8 31
rlm@8 32 // Local includes
rlm@8 33 `include "asim/provides/processor_library.bsh"
rlm@8 34 `include "asim/provides/mem_arb.bsh"
rlm@8 35 `include "asim/provides/instruction_cache.bsh"
rlm@8 36 `include "asim/provides/data_cache.bsh"
rlm@8 37 `include "asim/provides/processor.bsh"
rlm@8 38
rlm@8 39
rlm@8 40
rlm@8 41 interface Core;
rlm@8 42
rlm@8 43 // Interface from core to main memory
rlm@8 44 interface Client#(MainMemReq,MainMemResp) mmem_client;
rlm@8 45
rlm@8 46 endinterface
rlm@8 47
rlm@8 48 module [CONNECTED_MODULE] mkCore( Core );
rlm@8 49
rlm@8 50 // Instantiate the modules
rlm@8 51
rlm@8 52 Proc proc <- mkProc();
rlm@8 53 ICache#(InstReq,InstResp) icache <- mkInstCache();
rlm@8 54 DCache#(DataReq,DataResp) dcache <- mkDataCache();
rlm@8 55 MemArb marb <- mkMemArb();
rlm@8 56
rlm@8 57 // Internal connections
rlm@8 58
rlm@8 59 mkConnection( proc.statsEn_get, icache.statsEn_put );
rlm@8 60 mkConnection( proc.statsEn_get, dcache.statsEn_put );
rlm@8 61 mkConnection( proc.imem_client, icache.proc_server );
rlm@8 62 mkConnection( proc.dmem_client, dcache.proc_server );
rlm@8 63 mkConnection( icache.mmem_client, marb.cache0_server );
rlm@8 64 mkConnection( dcache.mmem_client, marb.cache1_server );
rlm@8 65
rlm@8 66 // Methods
rlm@8 67
rlm@8 68 interface mmem_client = marb.mmem_client;
rlm@8 69
rlm@8 70 endmodule