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rlm@8
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1 import CBusUtils::*;
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rlm@8
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2 import Register::*;
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3
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4 import Trace::*;
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5 import MemTypes::*;
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6 import IProc::*;
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7 import ProcTypes::*;
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8 import FPGATypes::*;
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9 import RegFile::*;
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10 import FIFO::*;
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11 import BFIFO::*;
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12 import Assert::*;
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13
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14 import GetPut::*;
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15 import GetPutExt::*;
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16 import ClientServer::*;
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17 import CBus::*;
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18
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19
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20 interface IProc;
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21
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22 // Interface for testrig
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23 interface Put#(Bit#(8)) testrig_fromhost;
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24 interface Get#(Bit#(8)) testrig_tohost;
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25
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26 // Interface from processor to caches
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27 interface Client#(DataReq,DataResp) dmem_client;
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28 interface Client#(InstReq,InstResp) imem_client;
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29
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30 // Interface for enabling/disabling statistics on the rest of the core
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31 interface Get#(Bool) statsEn_get;
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32
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33 endinterface
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34
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35
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36 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
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37
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38 //-----------------------------------------------------------
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39 // Register file module
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40 //-----------------------------------------------------------
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41
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42 interface RFile;
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43 method Action wr( Rindx rindx, Bit#(32) data );
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44 method Bit#(32) rd1( Rindx rindx );
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45 method Bit#(32) rd2( Rindx rindx );
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46 endinterface
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47
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48 module mkRFile( RFile );
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49
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50 RegFile#(Rindx,Bit#(32)) rfile <- mkRegFileFull();
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51
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52 method Action wr( Rindx rindx, Bit#(32) data );
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53 rfile.upd( rindx, data );
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54 endmethod
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55
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56 method Bit#(32) rd1( Rindx rindx );
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57 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
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58 endmethod
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59
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60 method Bit#(32) rd2( Rindx rindx );
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61 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
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62 endmethod
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63
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64 endmodule
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65
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66 //-----------------------------------------------------------
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67 // Helper functions
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68 //-----------------------------------------------------------
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69
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70 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
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71 return zeroExtend( pack( signedLT(val1,val2) ) );
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72 endfunction
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73
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74 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
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75 return zeroExtend( pack( val1 < val2 ) );
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76 endfunction
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77
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78 function Bit#(32) rshft( Bit#(32) val );
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79 return zeroExtend(val[4:0]);
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80 endfunction
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81
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82 //-----------------------------------------------------------
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83 // Reference processor
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84 //-----------------------------------------------------------
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85
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86
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87 module [ModWithCBus#(AvalonAddressWidth,AvalonDataWidth)] mkProc( IProc );
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88
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89 //-----------------------------------------------------------
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rlm@8
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90 // State
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91
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92 // Standard processor state
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93
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94 Reg#(Addr) pc <- mkReg(32'h00001000);
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95 Reg#(Stage) stage <- mkReg(PCgen);
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96 RFile rf <- mkRFile;
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97
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98 // Coprocessor state
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99
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100 Reg#(Bit#(8)) cp0_tohost <- mkReg(0);
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101 mkCBusWideRegRW(valueof(ToHostRegAddr),cp0_tohost);
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102 Reg#(Bit#(8)) cp0_fromhost <- mkReg(0);
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103 mkCBusWideRegRW(valueof(FromHostRegAddr),cp0_fromhost);
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104 Reg#(Bool) cp0_statsEn <- mkReg(False);
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105 mkCBusWideRegRW(valueof(StatsEnRegAddr),cp0_statsEn);
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rlm@8
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106 // Memory request/response state
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107
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108 FIFO#(InstReq) instReqQ <- mkBFIFO1();
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109 FIFO#(InstResp) instRespQ <- mkFIFO();
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110
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111 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
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112 FIFO#(DataResp) dataRespQ <- mkFIFO();
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113
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114 // Statistics state
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115
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116 Reg#(Int#(25)) num_cycles <- mkReg(25'h0);
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117 Reg#(Int#(25)) num_inst <- mkReg(25'h0);
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118
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119 //-----------------------------------------------------------
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120 // Rules
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121
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122 let pc_plus4 = pc + 4;
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123
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124 rule pcgen ( stage == PCgen );
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125 traceTiny("pc",pc);
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126 traceTiny("stage","P");
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127 instReqQ.enq( LoadReq{ addr:pc, tag:0 } );
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128 stage <= Exec;
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129 endrule
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130
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131 rule exec ( stage == Exec );
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132
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133 // Some abbreviations
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134 let sext = signExtend;
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135 let zext = zeroExtend;
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136 let sra = signedShiftRight;
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137
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138 // Get the instruction
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139
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140 instRespQ.deq();
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141 Instr inst
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142 = case ( instRespQ.first() ) matches
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143 tagged LoadResp .ld : return unpack(ld.data);
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144 tagged StoreResp .st : return ?;
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145 endcase;
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146
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147 // Some default variables
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148 Stage next_stage = PCgen;
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149 Addr next_pc = pc_plus4;
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150
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151 // Tracing
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152 traceTiny("stage","X");
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153 traceTiny("exInstTiny",inst);
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154 traceFull("exInstFull",inst);
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155
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156 case ( inst ) matches
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157
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158 // -- Memory Ops ------------------------------------------------
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159
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160 tagged LW .it :
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161 begin
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162 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
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163 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
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164 next_stage = Writeback;
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165 end
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166
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167 tagged SW .it :
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168 begin
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169 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
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170 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd1(it.rsrc) } );
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171 next_stage = Writeback;
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172 end
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173
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174 // -- Simple Ops ------------------------------------------------
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175
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176 tagged ADDIU .it : rf.wr( it.rdst, rf.rd1(it.rsrc) + sext(it.imm) );
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177 tagged SLTI .it : rf.wr( it.rdst, slt( rf.rd1(it.rsrc), sext(it.imm) ) );
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178 tagged SLTIU .it : rf.wr( it.rdst, sltu( rf.rd1(it.rsrc), sext(it.imm) ) );
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179 tagged ANDI .it :
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180 begin
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181 Bit#(32) zext_it_imm = zext(it.imm);
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182 rf.wr( it.rdst, rf.rd1(it.rsrc) & zext_it_imm );
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183 end
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184 tagged ORI .it :
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185 begin
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186 Bit#(32) zext_it_imm = zext(it.imm);
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187 rf.wr( it.rdst, rf.rd1(it.rsrc) | zext_it_imm );
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188 end
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189 tagged XORI .it :
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190 begin
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191 Bit#(32) zext_it_imm = zext(it.imm);
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192 rf.wr( it.rdst, rf.rd1(it.rsrc) ^ zext_it_imm );
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193 end
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rlm@8
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194 tagged LUI .it :
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195 begin
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196 Bit#(32) zext_it_imm = zext(it.imm);
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197 rf.wr( it.rdst, (zext_it_imm << 32'd16) );
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198 end
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199
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200 tagged SLL .it :
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201 begin
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202 Bit#(32) zext_it_shamt = zext(it.shamt);
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203 rf.wr( it.rdst, rf.rd1(it.rsrc) << zext_it_shamt );
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204 end
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205 tagged SRL .it :
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206 begin
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207 Bit#(32) zext_it_shamt = zext(it.shamt);
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208 rf.wr( it.rdst, rf.rd1(it.rsrc) >> zext_it_shamt );
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209 end
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210 tagged SRA .it :
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211 begin
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212 Bit#(32) zext_it_shamt = zext(it.shamt);
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213 rf.wr( it.rdst, sra( rf.rd1(it.rsrc), zext_it_shamt ));
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214 end
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215 tagged SLLV .it : rf.wr( it.rdst, rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) );
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216 tagged SRLV .it : rf.wr( it.rdst, rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) );
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217 tagged SRAV .it : rf.wr( it.rdst, sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) );
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218 tagged ADDU .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) );
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219 tagged SUBU .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) );
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220 tagged AND .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) );
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221 tagged OR .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) );
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222 tagged XOR .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) );
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223 tagged NOR .it : rf.wr( it.rdst, ~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) );
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224 tagged SLT .it : rf.wr( it.rdst, slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) );
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225 tagged SLTU .it : rf.wr( it.rdst, sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) );
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226
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227 // -- Branches --------------------------------------------------
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228
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229 tagged BLEZ .it :
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230 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
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231 next_pc = pc_plus4 + (sext(it.offset) << 2);
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232
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233 tagged BGTZ .it :
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234 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
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235 next_pc = pc_plus4 + (sext(it.offset) << 2);
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236
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237 tagged BLTZ .it :
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238 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
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239 next_pc = pc_plus4 + (sext(it.offset) << 2);
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240
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241 tagged BGEZ .it :
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242 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
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243 next_pc = pc_plus4 + (sext(it.offset) << 2);
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244
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245 tagged BEQ .it :
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246 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
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247 next_pc = pc_plus4 + (sext(it.offset) << 2);
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248
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249 tagged BNE .it :
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250 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
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251 next_pc = pc_plus4 + (sext(it.offset) << 2);
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252
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rlm@8
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253 // -- Jumps -----------------------------------------------------
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254
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255 tagged J .it :
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256 next_pc = { pc_plus4[31:28], it.target, 2'b0 };
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257
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258 tagged JR .it :
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259 next_pc = rf.rd1(it.rsrc);
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260
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261 tagged JAL .it :
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262 begin
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263 rf.wr( 31, pc_plus4 );
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264 next_pc = { pc_plus4[31:28], it.target, 2'b0 };
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265 end
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266
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267 tagged JALR .it :
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rlm@8
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268 begin
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269 rf.wr( it.rdst, pc_plus4 );
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rlm@8
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270 next_pc = rf.rd1(it.rsrc);
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271 end
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272
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rlm@8
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273 // -- Cop0 ------------------------------------------------------
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274
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275 tagged MTC0 .it :
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276 case ( it.cop0dst )
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277 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
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278 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
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279 default :
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280 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
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281 endcase
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282
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283 tagged MFC0 .it :
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284 case ( it.cop0src )
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285 5'd10 : rf.wr( it.rdst, zext(pack(cp0_statsEn)) );
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rlm@8
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286 5'd20 : rf.wr( it.rdst, zext(cp0_fromhost) );
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rlm@8
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287 5'd21 : rf.wr( it.rdst, zext(cp0_tohost) );
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288 default :
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289 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
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290 endcase
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291
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rlm@8
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292 // -- Illegal ---------------------------------------------------
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293
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294 default :
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295 $display( " RTL-ERROR : %m : Illegal instruction !" );
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rlm@8
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296
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rlm@8
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297 endcase
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rlm@8
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298
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rlm@8
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299 stage <= next_stage;
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rlm@8
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300 pc <= next_pc;
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rlm@8
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301
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rlm@8
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302 if ( cp0_statsEn )
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rlm@8
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303 num_inst <= num_inst + 1;
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rlm@8
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304
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rlm@8
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305 endrule
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rlm@8
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306
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rlm@8
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307 rule writeback ( stage == Writeback );
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rlm@8
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308 traceTiny("stage","W");
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rlm@8
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309
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rlm@8
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310 dataRespQ.deq();
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rlm@8
|
311 case ( dataRespQ.first() ) matches
|
|
rlm@8
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312 tagged LoadResp .ld : rf.wr( truncate(ld.tag), ld.data );
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rlm@8
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313 tagged StoreResp .st : noAction;
|
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rlm@8
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314 endcase
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rlm@8
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315
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rlm@8
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316 stage <= PCgen;
|
|
rlm@8
|
317 endrule
|
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rlm@8
|
318
|
|
rlm@8
|
319 rule inc_num_cycles;
|
|
rlm@8
|
320 if ( cp0_statsEn )
|
|
rlm@8
|
321 num_cycles <= num_cycles + 1;
|
|
rlm@8
|
322 endrule
|
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rlm@8
|
323
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|
rlm@8
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324 //-----------------------------------------------------------
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rlm@8
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325 // Methods
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rlm@8
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326
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rlm@8
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327 interface Client imem_client;
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rlm@8
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328 interface Get request = fifoToGet(instReqQ);
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|
rlm@8
|
329 interface Put response = fifoToPut(instRespQ);
|
|
rlm@8
|
330 endinterface
|
|
rlm@8
|
331
|
|
rlm@8
|
332 interface Client dmem_client;
|
|
rlm@8
|
333 interface Get request = fifoToGet(dataReqQ);
|
|
rlm@8
|
334 interface Put response = fifoToPut(dataRespQ);
|
|
rlm@8
|
335 endinterface
|
|
rlm@8
|
336
|
|
rlm@8
|
337 interface Get testrig_tohost = regToGet(cp0_tohost);
|
|
rlm@8
|
338 interface Put testrig_fromhost = regToPut(cp0_fromhost);
|
|
rlm@8
|
339 interface Get statsEn_get = regToGet(cp0_statsEn);
|
|
rlm@8
|
340
|
|
rlm@8
|
341 endmodule
|
|
rlm@8
|
342
|
