annotate modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv @ 51:9fe5ed4af92d pygar svn.52

[svn r52] tested having multiple cores
author punk
date Wed, 05 May 2010 17:01:04 -0400
parents 61f6267cb3db
children 6179c07c21d7
rev   line source
rlm@8 1 // The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@8 23 // Local includes
rlm@8 24 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8 25 `include "asim/provides/soft_connections.bsh"
rlm@8 26 `include "asim/provides/processor_library.bsh"
rlm@8 27 `include "asim/provides/fpga_components.bsh"
rlm@8 28 `include "asim/provides/common_services.bsh"
rlm@8 29
rlm@8 30 import Connectable::*;
rlm@8 31 import GetPut::*;
rlm@8 32 import ClientServer::*;
rlm@8 33 import RegFile::*;
rlm@8 34 import FIFO::*;
rlm@8 35 import FIFOF::*;
punk@28 36 import Trace::*;
rlm@8 37
rlm@8 38 interface DCache#( type req_t, type resp_t );
rlm@8 39
rlm@8 40 // Interface from processor to cache
rlm@8 41 interface Server#(req_t,resp_t) proc_server;
rlm@8 42
rlm@8 43 // Interface from cache to main memory
rlm@8 44 interface Client#(MainMemReq,MainMemResp) mmem_client;
rlm@8 45
rlm@8 46 // Interface for enabling/disabling statistics
rlm@8 47 interface Put#(Bool) statsEn_put;
rlm@8 48
rlm@8 49 endinterface
rlm@8 50
rlm@8 51
rlm@8 52 //----------------------------------------------------------------------
rlm@8 53 // Cache Types
rlm@8 54 //----------------------------------------------------------------------
rlm@8 55
rlm@8 56 typedef 10 CacheLineIndexSz;
rlm@8 57 typedef 20 CacheLineTagSz;
rlm@8 58 typedef 32 CacheLineSz;
rlm@8 59
rlm@8 60 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
rlm@8 61 typedef Bit#(CacheLineTagSz) CacheLineTag;
rlm@8 62 typedef Bit#(CacheLineSz) CacheLine;
rlm@8 63
rlm@8 64 typedef enum
rlm@8 65 {
rlm@8 66 Init,
rlm@8 67 Access,
rlm@8 68 RefillReq,
rlm@8 69 RefillResp
rlm@8 70 }
rlm@8 71 CacheStage
rlm@8 72 deriving (Eq,Bits);
rlm@8 73
rlm@8 74 //----------------------------------------------------------------------
rlm@8 75 // Helper functions
rlm@8 76 //----------------------------------------------------------------------
rlm@8 77
rlm@8 78 function Bit#(AddrSz) getAddr( DataReq req );
rlm@8 79
rlm@8 80 Bit#(AddrSz) addr = ?;
rlm@8 81 case ( req ) matches
rlm@8 82 tagged LoadReq .ld : addr = ld.addr;
rlm@8 83 tagged StoreReq .st : addr = st.addr;
rlm@8 84 endcase
rlm@8 85
rlm@8 86 return addr;
rlm@8 87
rlm@8 88 endfunction
rlm@8 89
rlm@8 90 function CacheLineIndex getCacheLineIndex( DataReq req );
rlm@8 91 Bit#(AddrSz) addr = getAddr(req);
rlm@8 92 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
rlm@8 93 return index;
rlm@8 94 endfunction
rlm@8 95
rlm@8 96 function CacheLineTag getCacheLineTag( DataReq req );
rlm@8 97 Bit#(AddrSz) addr = getAddr(req);
rlm@8 98 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
rlm@8 99 return tag;
rlm@8 100 endfunction
rlm@8 101
rlm@8 102 function Bit#(AddrSz) getCacheLineAddr( DataReq req );
rlm@8 103 Bit#(AddrSz) addr = getAddr(req);
rlm@8 104 return ((addr >> 2) << 2);
rlm@8 105 endfunction
rlm@8 106
rlm@8 107 //----------------------------------------------------------------------
rlm@8 108 // Main module
rlm@8 109 //----------------------------------------------------------------------
rlm@8 110
rlm@8 111 module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) );
rlm@8 112
rlm@8 113 //-----------------------------------------------------------
rlm@8 114 // State
rlm@8 115
rlm@8 116 Reg#(CacheStage) stage <- mkReg(Init);
rlm@8 117
rlm@8 118 LUTRAM#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkLUTRAMU_RegFile();
rlm@8 119 LUTRAM#(CacheLineIndex,CacheLine) cacheDataRam <- mkLUTRAMU_RegFile();
rlm@8 120
rlm@8 121 FIFO#(DataReq) reqQ <- mkFIFO();
rlm@8 122 FIFOF#(DataResp) respQ <- mkBFIFOF1();
rlm@8 123
rlm@8 124 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
rlm@8 125 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
rlm@8 126
rlm@8 127 Reg#(CacheLineIndex) initCounter <- mkReg(1);
rlm@8 128
rlm@8 129 // Statistics state
rlm@8 130
rlm@8 131 Reg#(Bool) statsEn <- mkReg(False);
rlm@49 132 //rlm:
rlm@49 133 //STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
rlm@49 134 //STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
rlm@49 135 //STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
rlm@8 136
rlm@8 137 //-----------------------------------------------------------
rlm@8 138 // Name some wires
rlm@8 139
rlm@8 140 let req = reqQ.first();
rlm@8 141 let reqIndex = getCacheLineIndex(req);
rlm@8 142 let reqTag = getCacheLineTag(req);
rlm@8 143 let reqCacheLineAddr = getCacheLineAddr(req);
rlm@8 144
rlm@8 145 //-----------------------------------------------------------
rlm@8 146 // Initialize
rlm@8 147
rlm@8 148 rule init ( stage == Init );
rlm@8 149 traceTiny("mkDataCacheBlocking", "stage","i");
rlm@8 150 initCounter <= initCounter + 1;
rlm@8 151 cacheTagRam.upd(initCounter,Invalid);
rlm@8 152 if ( initCounter == 0 )
rlm@8 153 stage <= Access;
rlm@8 154 endrule
rlm@8 155
rlm@8 156 //-----------------------------------------------------------
rlm@8 157 // Access cache rule
rlm@8 158
rlm@8 159 rule access ( (stage == Access) && respQ.notFull() );
rlm@8 160
rlm@8 161 // Statistics
rlm@49 162 //rlm:
rlm@49 163 //if ( statsEn )
rlm@49 164 // num_accesses.incr();
rlm@8 165
rlm@8 166
rlm@8 167 // Get the corresponding tag from the rams
rlm@8 168
rlm@8 169 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
rlm@8 170
rlm@8 171 // Handle cache hits ...
rlm@8 172
rlm@8 173 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
rlm@8 174 begin
rlm@8 175 traceTiny("mkDataCacheBlocking", "hitMiss","h");
rlm@8 176 reqQ.deq();
rlm@8 177
rlm@8 178 case ( req ) matches
rlm@8 179
rlm@8 180 tagged LoadReq .ld :
rlm@8 181 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } );
rlm@8 182
rlm@8 183 tagged StoreReq .st :
rlm@8 184 begin
rlm@8 185 respQ.enq( StoreResp { tag : st.tag } );
rlm@8 186 cacheDataRam.upd(reqIndex,st.data);
rlm@8 187 end
rlm@8 188
rlm@8 189 endcase
rlm@8 190
rlm@8 191 end
rlm@8 192
rlm@8 193 // Handle cache misses ...
rlm@8 194
rlm@8 195 else
rlm@8 196 begin
rlm@8 197 traceTiny("mkDataCacheBlocking", "hitMiss","m");
rlm@49 198 //rlm:
rlm@49 199 //if ( statsEn )
rlm@49 200 // num_misses.incr();
rlm@8 201
rlm@8 202 // Currently we don't use dirty bits so we always writeback the data if it is valid
rlm@8 203
rlm@8 204 if ( isValid(cacheLineTag) )
rlm@8 205 begin
rlm@49 206 //rlm:
rlm@49 207 // if ( statsEn )
rlm@49 208 // num_writebacks.incr();
rlm@8 209
rlm@8 210 MainMemReq wbReq
rlm@8 211 = StoreReq { tag : 0,
rlm@8 212 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },
rlm@8 213 data : cacheDataRam.sub(reqIndex) };
rlm@8 214
rlm@8 215 mainMemReqQ.enq(wbReq);
rlm@8 216 stage <= RefillReq;
rlm@8 217 end
rlm@8 218
rlm@8 219 // Otherwise we can issue the refill request now
rlm@8 220
rlm@8 221 else
rlm@8 222 begin
rlm@8 223 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
rlm@8 224 stage <= RefillResp;
rlm@8 225 end
rlm@8 226
rlm@8 227 end
rlm@8 228
rlm@8 229 endrule
rlm@8 230
rlm@8 231 //-----------------------------------------------------------
rlm@8 232 // Refill request rule
rlm@8 233
rlm@8 234 rule refillReq ( stage == RefillReq );
rlm@8 235 traceTiny("mkDataCacheBlocking", "stage","r");
rlm@8 236 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
rlm@8 237 stage <= RefillResp;
rlm@8 238 endrule
rlm@8 239
rlm@8 240 //-----------------------------------------------------------
rlm@8 241 // Refill response rule
rlm@8 242
rlm@8 243 rule refillResp ( stage == RefillResp );
rlm@8 244 traceTiny("mkDataCacheBlocking", "stage","R");
rlm@8 245 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first());
rlm@8 246
rlm@8 247 // Write the new data into the cache and update the tag
rlm@8 248
rlm@8 249 mainMemRespQ.deq();
rlm@8 250 case ( mainMemRespQ.first() ) matches
rlm@8 251
rlm@8 252 tagged LoadResp .ld :
rlm@8 253 begin
rlm@8 254 cacheTagRam.upd(reqIndex,Valid(reqTag));
rlm@8 255 cacheDataRam.upd(reqIndex,ld.data);
rlm@8 256 end
rlm@8 257
rlm@8 258 tagged StoreResp .st :
rlm@8 259 noAction;
rlm@8 260
rlm@8 261 endcase
rlm@8 262
rlm@8 263 stage <= Access;
rlm@8 264 endrule
rlm@8 265
rlm@8 266 //-----------------------------------------------------------
rlm@8 267 // Methods
rlm@8 268
rlm@8 269 interface Client mmem_client;
rlm@8 270 interface Get request = fifoToGet(mainMemReqQ);
rlm@8 271 interface Put response = fifoToPut(mainMemRespQ);
rlm@8 272 endinterface
rlm@8 273
rlm@8 274 interface Server proc_server;
rlm@8 275 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",fifoToPut(reqQ));
rlm@8 276 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",fifofToGet(respQ));
rlm@8 277 endinterface
rlm@8 278
rlm@8 279 interface Put statsEn_put = regToPut(statsEn);
rlm@8 280
rlm@8 281 endmodule