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annotate core/src/DataCacheBlocking.bsv @ 23:90197e3375e2 pygar svn.24

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[svn r24] added testing, but something is wrong with our c++ file.
author rlm
date Wed, 28 Apr 2010 08:19:09 -0400
parents 91a1f76ddd62
children
rev   line source
punk@1 1 // The MIT License
punk@1 2
punk@1 3 // Copyright (c) 2009 Massachusetts Institute of Technology
punk@1 4
punk@1 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@1 6 // of this software and associated documentation files (the "Software"), to deal
punk@1 7 // in the Software without restriction, including without limitation the rights
punk@1 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@1 9 // copies of the Software, and to permit persons to whom the Software is
punk@1 10 // furnished to do so, subject to the following conditions:
punk@1 11
punk@1 12 // The above copyright notice and this permission notice shall be included in
punk@1 13 // all copies or substantial portions of the Software.
punk@1 14
punk@1 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@1 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@1 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@1 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@1 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@1 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@1 21 // THE SOFTWARE.
punk@1 22
punk@1 23 import Connectable::*;
punk@1 24 import GetPut::*;
punk@1 25 import ClientServer::*;
punk@1 26 import RegFile::*;
punk@1 27 import FIFO::*;
punk@1 28 import FIFOF::*;
punk@1 29
punk@1 30 import BFIFO::*;
punk@1 31 import MemTypes::*;
punk@1 32 import ProcTypes::*;
punk@1 33 import Trace::*;
punk@1 34
punk@1 35 interface DCacheStats;
punk@1 36 interface Get#(Stat) num_accesses;
punk@1 37 interface Get#(Stat) num_misses;
punk@1 38 interface Get#(Stat) num_writebacks;
punk@1 39 endinterface
punk@1 40
punk@1 41 interface DCache#( type req_t, type resp_t );
punk@1 42
punk@1 43 // Interface from processor to cache
punk@1 44 interface Server#(req_t,resp_t) proc_server;
punk@1 45
punk@1 46 // Interface from cache to main memory
punk@1 47 interface Client#(MainMemReq,MainMemResp) mmem_client;
punk@1 48
punk@1 49 // Interface for enabling/disabling statistics
punk@1 50 interface Put#(Bool) statsEn_put;
punk@1 51
punk@1 52 // Interface for collecting statistics
punk@1 53 interface DCacheStats stats;
punk@1 54
punk@1 55 endinterface
punk@1 56
punk@1 57
punk@1 58 //----------------------------------------------------------------------
punk@1 59 // Cache Types
punk@1 60 //----------------------------------------------------------------------
punk@1 61
punk@1 62 typedef 10 CacheLineIndexSz;
punk@1 63 typedef 20 CacheLineTagSz;
punk@1 64 typedef 32 CacheLineSz;
punk@1 65
punk@1 66 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
punk@1 67 typedef Bit#(CacheLineTagSz) CacheLineTag;
punk@1 68 typedef Bit#(CacheLineSz) CacheLine;
punk@1 69
punk@1 70 typedef enum
punk@1 71 {
punk@1 72 Init,
punk@1 73 Access,
punk@1 74 RefillReq,
punk@1 75 RefillResp
punk@1 76 }
punk@1 77 CacheStage
punk@1 78 deriving (Eq,Bits);
punk@1 79
punk@1 80 //----------------------------------------------------------------------
punk@1 81 // Helper functions
punk@1 82 //----------------------------------------------------------------------
punk@1 83
punk@1 84 function Bit#(AddrSz) getAddr( DataReq req );
punk@1 85
punk@1 86 Bit#(AddrSz) addr = ?;
punk@1 87 case ( req ) matches
punk@1 88 tagged LoadReq .ld : addr = ld.addr;
punk@1 89 tagged StoreReq .st : addr = st.addr;
punk@1 90 endcase
punk@1 91
punk@1 92 return addr;
punk@1 93
punk@1 94 endfunction
punk@1 95
punk@1 96 function CacheLineIndex getCacheLineIndex( DataReq req );
punk@1 97 Bit#(AddrSz) addr = getAddr(req);
punk@1 98 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
punk@1 99 return index;
punk@1 100 endfunction
punk@1 101
punk@1 102 function CacheLineTag getCacheLineTag( DataReq req );
punk@1 103 Bit#(AddrSz) addr = getAddr(req);
punk@1 104 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
punk@1 105 return tag;
punk@1 106 endfunction
punk@1 107
punk@1 108 function Bit#(AddrSz) getCacheLineAddr( DataReq req );
punk@1 109 Bit#(AddrSz) addr = getAddr(req);
punk@1 110 return ((addr >> 2) << 2);
punk@1 111 endfunction
punk@1 112
punk@1 113 //----------------------------------------------------------------------
punk@1 114 // Main module
punk@1 115 //----------------------------------------------------------------------
punk@1 116
punk@1 117 (* doc = "synthesis attribute ram_style mkDataCache distributed;" *)
punk@1 118 (* synthesize *)
punk@1 119 module mkDataCache( DCache#(DataReq,DataResp) );
punk@1 120
punk@1 121 //-----------------------------------------------------------
punk@1 122 // State
punk@1 123
punk@1 124 Reg#(CacheStage) stage <- mkReg(Init);
punk@1 125
punk@1 126 RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull();
punk@1 127 RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull();
punk@1 128
punk@1 129 FIFO#(DataReq) reqQ <- mkFIFO();
punk@1 130 FIFOF#(DataResp) respQ <- mkBFIFOF1();
punk@1 131
punk@1 132 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
punk@1 133 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
punk@1 134
punk@1 135 Reg#(CacheLineIndex) initCounter <- mkReg(1);
punk@1 136
punk@1 137 // Statistics state
punk@1 138
punk@1 139 Reg#(Bool) statsEn <- mkReg(False);
punk@1 140
punk@1 141 Reg#(Stat) num_accesses <- mkReg(0);
punk@1 142 Reg#(Stat) num_misses <- mkReg(0);
punk@1 143 Reg#(Stat) num_writebacks <- mkReg(0);
punk@1 144
punk@1 145 //-----------------------------------------------------------
punk@1 146 // Name some wires
punk@1 147
punk@1 148 let req = reqQ.first();
punk@1 149 let reqIndex = getCacheLineIndex(req);
punk@1 150 let reqTag = getCacheLineTag(req);
punk@1 151 let reqCacheLineAddr = getCacheLineAddr(req);
punk@1 152
punk@1 153 //-----------------------------------------------------------
punk@1 154 // Initialize
punk@1 155
punk@1 156 rule init ( stage == Init );
punk@1 157 traceTiny("mkDataCacheBlocking", "stage","i");
punk@1 158 initCounter <= initCounter + 1;
punk@1 159 cacheTagRam.upd(initCounter,Invalid);
punk@1 160 if ( initCounter == 0 )
punk@1 161 stage <= Access;
punk@1 162 endrule
punk@1 163
punk@1 164 //-----------------------------------------------------------
punk@1 165 // Access cache rule
punk@1 166
punk@1 167 rule access ( (stage == Access) && respQ.notFull() );
punk@1 168
punk@1 169 // Statistics
punk@1 170
punk@1 171 if ( statsEn )
punk@1 172 num_accesses <= num_accesses + 1;
punk@1 173
punk@1 174
punk@1 175 // Get the corresponding tag from the rams
punk@1 176
punk@1 177 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
punk@1 178
punk@1 179 // Handle cache hits ...
punk@1 180
punk@1 181 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
punk@1 182 begin
punk@1 183 traceTiny("mkDataCacheBlocking", "hitMiss","h");
punk@1 184 reqQ.deq();
punk@1 185
punk@1 186 case ( req ) matches
punk@1 187
punk@1 188 tagged LoadReq .ld :
punk@1 189 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } );
punk@1 190
punk@1 191 tagged StoreReq .st :
punk@1 192 begin
punk@1 193 respQ.enq( StoreResp { tag : st.tag } );
punk@1 194 cacheDataRam.upd(reqIndex,st.data);
punk@1 195 end
punk@1 196
punk@1 197 endcase
punk@1 198
punk@1 199 end
punk@1 200
punk@1 201 // Handle cache misses ...
punk@1 202
punk@1 203 else
punk@1 204 begin
punk@1 205 traceTiny("mkDataCacheBlocking", "hitMiss","m");
punk@1 206 if ( statsEn )
punk@1 207 num_misses <= num_misses + 1;
punk@1 208
punk@1 209 // Currently we don't use dirty bits so we always writeback the data if it is valid
punk@1 210
punk@1 211 if ( isValid(cacheLineTag) )
punk@1 212 begin
punk@1 213
punk@1 214 if ( statsEn )
punk@1 215 num_writebacks <= num_writebacks + 1;
punk@1 216
punk@1 217 MainMemReq wbReq
punk@1 218 = StoreReq { tag : 0,
punk@1 219 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },
punk@1 220 data : cacheDataRam.sub(reqIndex) };
punk@1 221
punk@1 222 mainMemReqQ.enq(wbReq);
punk@1 223 stage <= RefillReq;
punk@1 224 end
punk@1 225
punk@1 226 // Otherwise we can issue the refill request now
punk@1 227
punk@1 228 else
punk@1 229 begin
punk@1 230 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
punk@1 231 stage <= RefillResp;
punk@1 232 end
punk@1 233
punk@1 234 end
punk@1 235
punk@1 236 endrule
punk@1 237
punk@1 238 //-----------------------------------------------------------
punk@1 239 // Refill request rule
punk@1 240
punk@1 241 rule refillReq ( stage == RefillReq );
punk@1 242 traceTiny("mkDataCacheBlocking", "stage","r");
punk@1 243 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
punk@1 244 stage <= RefillResp;
punk@1 245 endrule
punk@1 246
punk@1 247 //-----------------------------------------------------------
punk@1 248 // Refill response rule
punk@1 249
punk@1 250 rule refillResp ( stage == RefillResp );
punk@1 251 traceTiny("mkDataCacheBlocking", "stage","R");
punk@1 252 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first());
punk@1 253
punk@1 254 // Write the new data into the cache and update the tag
punk@1 255
punk@1 256 mainMemRespQ.deq();
punk@1 257 case ( mainMemRespQ.first() ) matches
punk@1 258
punk@1 259 tagged LoadResp .ld :
punk@1 260 begin
punk@1 261 cacheTagRam.upd(reqIndex,Valid(reqTag));
punk@1 262 cacheDataRam.upd(reqIndex,ld.data);
punk@1 263 end
punk@1 264
punk@1 265 tagged StoreResp .st :
punk@1 266 noAction;
punk@1 267
punk@1 268 endcase
punk@1 269
punk@1 270 stage <= Access;
punk@1 271 endrule
punk@1 272
punk@1 273 //-----------------------------------------------------------
punk@1 274 // Methods
punk@1 275
punk@1 276 interface Client mmem_client;
punk@1 277 interface Get request = toGet(mainMemReqQ);
punk@1 278 interface Put response = toPut(mainMemRespQ);
punk@1 279 endinterface
punk@1 280
punk@1 281 interface Server proc_server;
punk@1 282 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",toPut(reqQ));
punk@1 283 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",toGet(respQ));
punk@1 284 endinterface
punk@1 285
punk@1 286 interface Put statsEn_put = toPut(asReg(statsEn));
punk@1 287
punk@1 288 interface DCacheStats stats;
punk@1 289 interface Get num_accesses = toGet(asReg(num_accesses));
punk@1 290 interface Get num_misses = toGet(asReg(num_misses));
punk@1 291 interface Get num_writebacks = toGet(asReg(num_writebacks));
punk@1 292 endinterface
punk@1 293
punk@1 294 endmodule
punk@1 295