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annotate core/src/InstCacheBlocking.bsv @ 76:8bd0e4d37ad2 pygar svn.77 tip

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[svn r77] I don't know why my last change didn't go through grumble grumble....
author rlm
date Wed, 12 May 2010 08:58:23 -0400
parents 91a1f76ddd62
children
rev   line source
punk@1 1 // The MIT License
punk@1 2
punk@1 3 // Copyright (c) 2009 Massachusetts Institute of Technology
punk@1 4
punk@1 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@1 6 // of this software and associated documentation files (the "Software"), to deal
punk@1 7 // in the Software without restriction, including without limitation the rights
punk@1 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@1 9 // copies of the Software, and to permit persons to whom the Software is
punk@1 10 // furnished to do so, subject to the following conditions:
punk@1 11
punk@1 12 // The above copyright notice and this permission notice shall be included in
punk@1 13 // all copies or substantial portions of the Software.
punk@1 14
punk@1 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@1 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@1 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@1 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@1 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@1 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@1 21 // THE SOFTWARE.
punk@1 22
punk@1 23 import Connectable::*;
punk@1 24 import GetPut::*;
punk@1 25 import ClientServer::*;
punk@1 26 import RegFile::*;
punk@1 27 import FIFO::*;
punk@1 28 import FIFOF::*;
punk@1 29 import RWire::*;
punk@1 30
punk@1 31 import BFIFO::*;
punk@1 32 import MemTypes::*;
punk@1 33 import ProcTypes::*;
punk@1 34 import Trace::*;
punk@1 35
punk@1 36 interface ICacheStats;
punk@1 37 interface Get#(Stat) num_accesses;
punk@1 38 interface Get#(Stat) num_misses;
punk@1 39 interface Get#(Stat) num_evictions;
punk@1 40 endinterface
punk@1 41
punk@1 42 interface ICache#( type req_t, type resp_t );
punk@1 43
punk@1 44 // Interface from processor to cache
punk@1 45 interface Server#(req_t,resp_t) proc_server;
punk@1 46
punk@1 47 // Interface from cache to main memory
punk@1 48 interface Client#(MainMemReq,MainMemResp) mmem_client;
punk@1 49
punk@1 50 // Interface for enabling/disabling statistics
punk@1 51 interface Put#(Bool) statsEn_put;
punk@1 52
punk@1 53 // Interface for collecting statistics
punk@1 54 interface ICacheStats stats;
punk@1 55
punk@1 56 endinterface
punk@1 57
punk@1 58 //----------------------------------------------------------------------
punk@1 59 // Cache Types
punk@1 60 //----------------------------------------------------------------------
punk@1 61
punk@1 62 typedef 10 CacheLineIndexSz;
punk@1 63 typedef 20 CacheLineTagSz;
punk@1 64 typedef 32 CacheLineSz;
punk@1 65
punk@1 66 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
punk@1 67 typedef Bit#(CacheLineTagSz) CacheLineTag;
punk@1 68 typedef Bit#(CacheLineSz) CacheLine;
punk@1 69
punk@1 70 typedef enum
punk@1 71 {
punk@1 72 Init,
punk@1 73 Access,
punk@1 74 Evict,
punk@1 75 RefillReq,
punk@1 76 RefillResp
punk@1 77 }
punk@1 78 CacheStage
punk@1 79 deriving (Eq,Bits);
punk@1 80
punk@1 81 //----------------------------------------------------------------------
punk@1 82 // Helper functions
punk@1 83 //----------------------------------------------------------------------
punk@1 84
punk@1 85 function Bit#(AddrSz) getAddr( InstReq req );
punk@1 86
punk@1 87 Bit#(AddrSz) addr = ?;
punk@1 88 case ( req ) matches
punk@1 89 tagged LoadReq .ld : addr = ld.addr;
punk@1 90 tagged StoreReq .st : addr = st.addr;
punk@1 91 endcase
punk@1 92
punk@1 93 return addr;
punk@1 94
punk@1 95 endfunction
punk@1 96
punk@1 97 function CacheLineIndex getCacheLineIndex( InstReq req );
punk@1 98 Bit#(AddrSz) addr = getAddr(req);
punk@1 99 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
punk@1 100 return index;
punk@1 101 endfunction
punk@1 102
punk@1 103 function CacheLineTag getCacheLineTag( InstReq req );
punk@1 104 Bit#(AddrSz) addr = getAddr(req);
punk@1 105 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
punk@1 106 return tag;
punk@1 107 endfunction
punk@1 108
punk@1 109 function Bit#(AddrSz) getCacheLineAddr( InstReq req );
punk@1 110 Bit#(AddrSz) addr = getAddr(req);
punk@1 111 return ((addr >> 2) << 2);
punk@1 112 endfunction
punk@1 113
punk@1 114 //----------------------------------------------------------------------
punk@1 115 // Main module
punk@1 116 //----------------------------------------------------------------------
punk@1 117
punk@1 118 (* doc = "synthesis attribute ram_style mkInstCache distributed;" *)
punk@1 119 (* synthesize *)
punk@1 120 module mkInstCache( ICache#(InstReq,InstResp) );
punk@1 121
punk@1 122 //-----------------------------------------------------------
punk@1 123 // State
punk@1 124
punk@1 125 Reg#(CacheStage) stage <- mkReg(Init);
punk@1 126
punk@1 127 RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull();
punk@1 128 RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull();
punk@1 129
punk@1 130 FIFO#(InstReq) reqQ <- mkFIFO();
punk@1 131 FIFOF#(InstResp) respQ <- mkBFIFOF1();
punk@1 132
punk@1 133 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
punk@1 134 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
punk@1 135
punk@1 136 Reg#(CacheLineIndex) initCounter <- mkReg(1);
punk@1 137
punk@1 138 // Statistics state
punk@1 139
punk@1 140 Reg#(Bool) statsEn <- mkReg(False);
punk@1 141
punk@1 142 Reg#(Stat) numAccesses <- mkReg(0);
punk@1 143 Reg#(Stat) numMisses <- mkReg(0);
punk@1 144 Reg#(Stat) numEvictions <- mkReg(0);
punk@1 145
punk@1 146 //-----------------------------------------------------------
punk@1 147 // Name some wires
punk@1 148
punk@1 149 let req = reqQ.first();
punk@1 150 let reqIndex = getCacheLineIndex(req);
punk@1 151 let reqTag = getCacheLineTag(req);
punk@1 152 let reqCacheLineAddr = getCacheLineAddr(req);
punk@1 153 let refill = mainMemRespQ.first();
punk@1 154
punk@1 155 //-----------------------------------------------------------
punk@1 156 // Initialize
punk@1 157
punk@1 158 rule init ( stage == Init );
punk@1 159 traceTiny("mkInstCacheBlocking", "stage","i");
punk@1 160 initCounter <= initCounter + 1;
punk@1 161 cacheTagRam.upd(initCounter,Invalid);
punk@1 162 if ( initCounter == 0 )
punk@1 163 stage <= Access;
punk@1 164 endrule
punk@1 165
punk@1 166 //-----------------------------------------------------------
punk@1 167 // Cache access rule
punk@1 168
punk@1 169 rule access ( (stage == Access) && respQ.notFull() );
punk@1 170
punk@1 171 // Statistics
punk@1 172
punk@1 173 if ( statsEn )
punk@1 174 numAccesses <= numAccesses + 1;
punk@1 175
punk@1 176 // Check tag and valid bit to see if this is a hit or a miss
punk@1 177
punk@1 178 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
punk@1 179
punk@1 180 // Handle cache hits ...
punk@1 181
punk@1 182 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
punk@1 183 begin
punk@1 184 traceTiny("mkInstCacheBlocking", "hitMiss","h");
punk@1 185 reqQ.deq();
punk@1 186
punk@1 187 case ( req ) matches
punk@1 188
punk@1 189 tagged LoadReq .ld :
punk@1 190 respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } );
punk@1 191
punk@1 192 tagged StoreReq .st :
punk@1 193 $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" );
punk@1 194
punk@1 195 endcase
punk@1 196
punk@1 197 end
punk@1 198
punk@1 199 // Handle cache misses - since lines in instruction cache are
punk@1 200 // never dirty we can always immediately issue a refill request
punk@1 201
punk@1 202 else
punk@1 203 begin
punk@1 204 traceTiny("mkInstCacheBlocking", "hitMiss","m");
punk@1 205 if ( statsEn )
punk@1 206 numMisses <= numMisses + 1;
punk@1 207 if ( statsEn )
punk@1 208 if ( isJust(cacheLineTag) )
punk@1 209 numEvictions <= numEvictions + 1;
punk@1 210
punk@1 211 MainMemReq rfReq
punk@1 212 = LoadReq { tag : 0,
punk@1 213 addr : reqCacheLineAddr };
punk@1 214
punk@1 215 mainMemReqQ.enq(rfReq);
punk@1 216 stage <= RefillResp;
punk@1 217 end
punk@1 218
punk@1 219 endrule
punk@1 220
punk@1 221 //-----------------------------------------------------------
punk@1 222 // Refill response rule
punk@1 223
punk@1 224 rule refillResp ( stage == RefillResp );
punk@1 225 traceTiny("mkInstCacheBlocking", "stage","R");
punk@1 226 traceTiny("mkInstCacheBlocking", "refill",refill);
punk@1 227
punk@1 228 // Write the new data into the cache and update the tag
punk@1 229
punk@1 230 mainMemRespQ.deq();
punk@1 231 case ( mainMemRespQ.first() ) matches
punk@1 232
punk@1 233 tagged LoadResp .ld :
punk@1 234 begin
punk@1 235 cacheTagRam.upd(reqIndex,Valid(reqTag));
punk@1 236 cacheDataRam.upd(reqIndex,ld.data);
punk@1 237 end
punk@1 238
punk@1 239 tagged StoreResp .st :
punk@1 240 noAction;
punk@1 241
punk@1 242 endcase
punk@1 243
punk@1 244 stage <= Access;
punk@1 245 endrule
punk@1 246
punk@1 247 //-----------------------------------------------------------
punk@1 248 // Methods
punk@1 249
punk@1 250 interface Client mmem_client;
punk@1 251 interface Get request = fifoToGet(mainMemReqQ);
punk@1 252 interface Put response = fifoToPut(mainMemRespQ);
punk@1 253 endinterface
punk@1 254
punk@1 255 interface Server proc_server;
punk@1 256 interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",toPut(reqQ));
punk@1 257 interface Get response = traceGet("mkInstCacheBlocking", "respTiny",toGet(respQ));
punk@1 258 endinterface
punk@1 259
punk@1 260 interface Put statsEn_put = toPut(asReg(statsEn));
punk@1 261
punk@1 262 interface ICacheStats stats;
punk@1 263 interface Get num_accesses = toGet(asReg(numAccesses));
punk@1 264 interface Get num_misses = toGet(asReg(numMisses));
punk@1 265 interface Get num_evictions = toGet(asReg(numEvictions));
punk@1 266 endinterface
punk@1 267
punk@1 268 endmodule
punk@1 269