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1
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2 import ClientServer::*;
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3 import FIFO::*;
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4 import GetPut::*;
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5 import DefaultValue::*;
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6 import SceMi::*;
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7 import Clocks::*;
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8
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9 import Core::*;
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10 import ProcTypes::*;
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11 import Processor::*;
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12 import DataCacheBlocking::*;
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13 import InstCacheBlocking::*;
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14
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15 interface DutWrapper;
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16 interface Core core;
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17
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18 // We use a Bit#(1) instead of void because Bluespec Sce-Mi doesn't appear
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19 // to support sending void over the PCIe link yet.
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20 interface Put#(Bit#(1)) doreset;
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21 endinterface
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22
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23 (* synthesize *)
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24 module [Module] mkDutWrapper (DutWrapper);
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25
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26 Clock clk <- exposeCurrentClock;
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27 MakeResetIfc myrst <- mkReset(2000, True, clk);
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28
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29 Core coreifc <- mkCore(reset_by myrst.new_rst);
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30
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31 // For tracing
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32 Reg#(int) cycle <- mkReg(0);
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33 rule printCycles;
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34 cycle <= cycle + 1;
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35 $fdisplay(stderr, " => Cycle = %d", cycle);
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36 endrule
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37
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38 interface Core core = coreifc;
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39
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40 interface Put doreset;
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41 method Action put(Bit#(1) x);
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42 cycle <= 0;
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43 myrst.assertReset();
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44 endmethod
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45 endinterface
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46
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47 endmodule
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48
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49 module [SceMiModule] mkSceMiLayer();
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50
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51 SceMiClockConfiguration conf = defaultValue;
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52
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53 SceMiClockPortIfc clk_port <- mkSceMiClockPort(conf);
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54 DutWrapper dut <- buildDut(mkDutWrapper, clk_port);
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55
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56 Empty mmem <- mkClientXactor(dut.core.mmem_client, clk_port);
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57 Empty tohost <- mkCPUToHostXactor(dut.core.tohost, clk_port);
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58 Empty stats <- mkCoreStatsXactor(dut.core.stats, clk_port);
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59 Empty doreset <- mkPutXactor(dut.doreset, clk_port);
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60
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61 Empty shutdown <- mkShutdownXactor();
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62
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63 endmodule
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64
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65 module [SceMiModule] mkCPUToHostXactor#(CPUToHost tohost, SceMiClockPortIfc clk_port ) (Empty);
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66
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67 // Access the controlled clock and reset
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68 Clock cclock = clk_port.cclock;
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69 Reset creset = clk_port.creset;
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70
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71 // req belongs entirely to the controlled clock domain. We'll use the
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72 // clock domain crossings already implemented by the Bluespec people (in
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73 // the Put and Get transactors), because they know about such things
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74 // better than I do.
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75 FIFO#(int) req <- mkFIFO(clocked_by cclock, reset_by creset);
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76
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77 Get#(Bit#(32)) resp = interface Get;
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78 method ActionValue#(Bit#(32)) get();
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79 req.deq();
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80 return tohost.cpuToHost(req.first());
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81 endmethod
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82 endinterface;
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83
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84 Empty request <- mkPutXactor(toPut(req), clk_port);
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85 Empty response <- mkGetXactor(resp, clk_port);
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86
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87 endmodule
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88
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89 typedef enum {
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90 DCACHE_ACCESSES, DCACHE_MISSES, DCACHE_WRITEBACKS,
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91 ICACHE_ACCESSES, ICACHE_MISSES, ICACHE_EVICTIONS,
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92 PROC_INST, PROC_CYCLES
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93 } StatID deriving(Bits, Eq);
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94
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95 module [SceMiModule] mkCoreStatsXactor#(CoreStats stats, SceMiClockPortIfc clk_port) (Empty);
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96
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97 // Access the controlled clock and reset
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98 Clock cclock = clk_port.cclock;
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99 Reset creset = clk_port.creset;
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100
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101 // Again, req and resp belong to the controlled clock domain.
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102 FIFO#(StatID) req <- mkFIFO(clocked_by cclock, reset_by creset);
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103 FIFO#(Stat) resp <- mkFIFO(clocked_by cclock, reset_by creset);
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104
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105 rule handleRequest (True);
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106 case (req.first())
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107 DCACHE_ACCESSES: begin
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108 let x <- stats.dcache.num_accesses.get();
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109 resp.enq(x);
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110 end
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111 DCACHE_MISSES: begin
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112 let x <- stats.dcache.num_misses.get();
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113 resp.enq(x);
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114 end
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115 DCACHE_WRITEBACKS: begin
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116 let x <- stats.dcache.num_writebacks.get();
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117 resp.enq(x);
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118 end
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119 ICACHE_ACCESSES: begin
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120 let x <- stats.icache.num_accesses.get();
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121 resp.enq(x);
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122 end
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123 ICACHE_MISSES: begin
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124 let x <- stats.icache.num_misses.get();
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125 resp.enq(x);
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126 end
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127 ICACHE_EVICTIONS: begin
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128 let x <- stats.icache.num_evictions.get();
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129 resp.enq(x);
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130 end
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131 PROC_INST: begin
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132 let x <- stats.proc.num_inst.get();
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133 resp.enq(x);
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134 end
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135 PROC_CYCLES: begin
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136 let x <- stats.proc.num_cycles.get();
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137 resp.enq(x);
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138 end
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139 endcase
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140 req.deq();
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141 endrule
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142
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143 Server#(StatID, Stat) server = interface Server;
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144 interface Get response = toGet(resp);
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145 interface Put request = toPut(req);
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146 endinterface;
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147
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148 Empty xx <- mkServerXactor(server, clk_port);
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149 endmodule
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150
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