annotate modules/bluespec/Pygar/core/Processor.bsv @ 71:86360c5ae9f2 pygar svn.72

[svn r72] added config for htg
author punk
date Wed, 12 May 2010 00:21:40 -0400
parents 44cc00df1168
children
rev   line source
punk@51 1 // The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@19 23
rlm@8 24 import Connectable::*;
rlm@8 25 import GetPut::*;
rlm@8 26 import ClientServer::*;
rlm@8 27 import RegFile::*;
rlm@8 28
rlm@8 29 import FIFO::*;
rlm@8 30 import FIFOF::*;
rlm@8 31 import SFIFO::*;
rlm@8 32 import RWire::*;
rlm@8 33
punk@11 34 import Trace::*;
rlm@8 35 import BFIFO::*;
rlm@8 36 import MemTypes::*;
rlm@8 37 import ProcTypes::*;
rlm@8 38 import BRegFile::*;
rlm@8 39 import BranchPred::*;
rlm@8 40
rlm@8 41 //AWB includes
rlm@8 42 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8 43 `include "asim/provides/soft_connections.bsh"
rlm@8 44 `include "asim/provides/common_services.bsh"
rlm@8 45
rlm@8 46 // Local includes
punk@11 47 //`include "asim/provides/processor_library.bsh" (included above directly)
punk@36 48
rlm@8 49 `include "asim/provides/common_services.bsh"
punk@26 50 `include "asim/provides/processor_library.bsh"
rlm@8 51
punk@11 52 // Local includes. Look for the correspondingly named .awb files
punk@11 53 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@11 54 // to find the actual Bluespec files which are used to generate
punk@11 55 // these includes. These files are specific to this audio processing
punk@11 56 // pipeline
punk@11 57
punk@12 58 `include "asim/provides/audio_pipe_types.bsh"
punk@68 59 `include "asim/provides/path_types.bsh"
rlm@8 60
punk@12 61 //interface CPUToHost;
punk@12 62 // method Bit#(32) cpuToHost(int req);
punk@12 63 //endinterface
rlm@8 64
rlm@8 65 interface Proc;
rlm@8 66
rlm@8 67 // Interface from processor to caches
rlm@8 68 interface Client#(DataReq,DataResp) dmem_client;
rlm@8 69 interface Client#(InstReq,InstResp) imem_client;
rlm@8 70
rlm@8 71 // Interface for enabling/disabling statistics on the rest of the core
rlm@8 72 interface Get#(Bool) statsEn_get;
rlm@8 73
punk@68 74 // Interface to host
punk@68 75 interface Get#(Bit#(32)) pcCount;
rlm@8 76
punk@11 77 // Interface to Audio Pipeline
punk@68 78 interface Get#(AudioStream) sampleOutput;
punk@68 79 interface Put#(AudioStream) sampleInput;
punk@11 80
rlm@8 81 endinterface
rlm@8 82
rlm@8 83 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
rlm@8 84
rlm@8 85 //-----------------------------------------------------------
rlm@8 86 // Helper functions
rlm@8 87 //-----------------------------------------------------------
rlm@8 88
rlm@8 89 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
rlm@8 90 return zeroExtend( pack( signedLT(val1,val2) ) );
rlm@8 91 endfunction
rlm@8 92
rlm@8 93 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
rlm@8 94 return zeroExtend( pack( val1 < val2 ) );
rlm@8 95 endfunction
rlm@8 96
rlm@8 97 function Bit#(32) rshft( Bit#(32) val );
rlm@8 98 return zeroExtend(val[4:0]);
rlm@8 99 endfunction
rlm@8 100
rlm@8 101
rlm@8 102 //-----------------------------------------------------------
rlm@8 103 // Find funct for wbQ
rlm@8 104 //-----------------------------------------------------------
rlm@8 105 function Bool findwbf(Rindx fVal, WBResult cmpVal);
rlm@8 106 case (cmpVal) matches
rlm@8 107 tagged WB_ALU {data:.res, dest:.rd} :
rlm@8 108 return (fVal == rd);
rlm@8 109 tagged WB_Load .rd :
rlm@8 110 return (fVal == rd);
rlm@8 111 tagged WB_Store .st :
rlm@8 112 return False;
rlm@8 113 tagged WB_Host .x :
rlm@8 114 return False;
rlm@8 115 endcase
rlm@8 116 endfunction
rlm@8 117
rlm@8 118
rlm@8 119 //-----------------------------------------------------------
rlm@8 120 // Stall funct for wbQ
rlm@8 121 //-----------------------------------------------------------
rlm@8 122 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
rlm@8 123 case (inst) matches
rlm@8 124 // -- Memory Ops ------------------------------------------------
rlm@8 125 tagged LW .it :
rlm@8 126 return f.find(it.rbase);
rlm@8 127 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
rlm@8 128 return (f.find(addr) || f.find2(dreg));
rlm@8 129
rlm@8 130 // -- Simple Ops ------------------------------------------------
rlm@8 131 tagged ADDIU .it : return f.find(it.rsrc);
rlm@8 132 tagged SLTI .it : return f.find(it.rsrc);
rlm@8 133 tagged SLTIU .it : return f.find(it.rsrc);
rlm@8 134 tagged ANDI .it : return f.find(it.rsrc);
rlm@8 135 tagged ORI .it : return f.find(it.rsrc);
rlm@8 136 tagged XORI .it : return f.find(it.rsrc);
rlm@8 137
rlm@8 138 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
rlm@8 139 tagged SLL .it : return f.find(it.rsrc);
rlm@8 140 tagged SRL .it : return f.find(it.rsrc);
rlm@8 141 tagged SRA .it : return f.find(it.rsrc);
rlm@8 142 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 143 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 144 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 145 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 146 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 147 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 148 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 149 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 150 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 151 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 152 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 153
rlm@8 154
rlm@8 155 // -- Branches --------------------------------------------------
rlm@8 156
rlm@8 157 tagged BLEZ .it : return (f.find(it.rsrc));
rlm@8 158 tagged BGTZ .it : return (f.find(it.rsrc));
rlm@8 159 tagged BLTZ .it : return (f.find(it.rsrc));
rlm@8 160 tagged BGEZ .it : return (f.find(it.rsrc));
rlm@8 161 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 162 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 163
rlm@8 164 // -- Jumps -----------------------------------------------------
rlm@8 165
rlm@8 166 tagged J .it : return False;
rlm@8 167 tagged JR .it : return f.find(it.rsrc);
rlm@8 168 tagged JALR .it : return f.find(it.rsrc);
rlm@8 169 tagged JAL .it : return False;
rlm@8 170
rlm@8 171 // -- Cop0 ------------------------------------------------------
rlm@8 172
rlm@8 173 tagged MTC0 .it : return f.find(it.rsrc);
rlm@8 174 tagged MFC0 .it : return False;
rlm@8 175
rlm@8 176 // -- Illegal ---------------------------------------------------
rlm@8 177
rlm@8 178 default : return False;
rlm@8 179
rlm@8 180 endcase
rlm@8 181 endfunction
punk@68 182
punk@68 183
rlm@8 184 //-----------------------------------------------------------
rlm@8 185 // Reference processor
rlm@8 186 //-----------------------------------------------------------
rlm@8 187
rlm@8 188
rlm@8 189 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
rlm@8 190 //(* synthesize *)
rlm@8 191
punk@51 192 module mkProc( Proc );
rlm@8 193
rlm@8 194 //-----------------------------------------------------------
rlm@8 195 // State
rlm@8 196
rlm@8 197 // Standard processor state
rlm@8 198
rlm@8 199 Reg#(Addr) pc <- mkReg(32'h00001000);
rlm@8 200 Reg#(Epoch) epoch <- mkReg(0);
rlm@8 201 Reg#(Stage) stage <- mkReg(PCgen);
punk@63 202 BRegFile rf <- mkBRegFile;
rlm@8 203
rlm@8 204 // Branch Prediction
rlm@8 205 BranchPred bp <- mkBranchPred();
rlm@8 206 FIFO#(PCStat) execpc <- mkLFIFO();
rlm@8 207
rlm@8 208 // Pipelines
rlm@8 209 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
rlm@8 210 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
rlm@8 211
punk@33 212 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
rlm@8 213 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
rlm@8 214 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
rlm@8 215 Reg#(Bool) cp0_statsEn <- mkReg(False);
punk@33 216 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
punk@33 217 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
punk@68 218
punk@68 219 Reg#(Bool) code_bypass <- mkReg(True); // Register to enable passing invalid packets once all valid ones are passed OUT
punk@68 220 // (this becomes false at first valid packet)
punk@33 221
rlm@8 222 // Memory request/response state
rlm@8 223
rlm@8 224 FIFO#(InstReq) instReqQ <- mkBFIFO1();
rlm@8 225 FIFO#(InstResp) instRespQ <- mkFIFO();
rlm@8 226
rlm@8 227 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
rlm@8 228 FIFO#(DataResp) dataRespQ <- mkFIFO();
rlm@8 229
punk@11 230 // Audio I/O
punk@68 231 FIFO#(AudioStream) inAudioFifo <- mkSizedFIFO(512);
punk@68 232 FIFO#(AudioStream) outAudioFifo <- mkFIFO;
punk@68 233 Reg#(VoiceId) channel <-mkReg(0); // Set based on the reading the incoming data. Not entirely sure I like this. What if the program generates samples?
punk@11 234
punk@11 235 // Statistics state (2010)
rlm@35 236 // Reg#(Stat) num_cycles <- mkReg(0);
rlm@35 237 // Reg#(Stat) num_inst <- mkReg(0);
rlm@8 238
rlm@8 239 //Or:
punk@11 240 // Statistics state
rlm@49 241
rlm@49 242 //rlm: removing these to avoid their broken stupidness.
rlm@49 243 //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
rlm@49 244 //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
rlm@8 245
rlm@8 246 //-----------------------------------------------------------
punk@68 247 // Internal Functions
punk@68 248
punk@68 249 function Bool stallMTCO_MFCO(Instr inst);
punk@68 250 case(inst) matches
punk@68 251 tagged MTC0 .it :
punk@68 252 begin
punk@68 253 case (it.cop0dst)
punk@68 254 5'd26 : return cp0_progComp; // If true, processor service sendEnd which clears it.
punk@68 255 endcase
punk@68 256 end
punk@68 257 endcase
punk@68 258 endfunction
punk@68 259
punk@68 260 //-----------------------------------------------------------
rlm@8 261 // Rules
rlm@8 262
rlm@8 263 (* descending_urgency = "exec, pcgen" *)
rlm@8 264 rule pcgen; //( stage == PCgen );
rlm@8 265 let pc_plus4 = pc + 4;
rlm@8 266
rlm@8 267 traceTiny("mkProc", "pc",pc);
rlm@8 268 traceTiny("mkProc", "pcgen","P");
rlm@8 269 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
rlm@8 270
rlm@8 271 let next_pc = bp.get(pc);
rlm@8 272 if (next_pc matches tagged Valid .npc)
rlm@8 273 begin
rlm@8 274 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
rlm@8 275 pc <= npc;
rlm@8 276 end
rlm@8 277 else
rlm@8 278 begin
rlm@8 279 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
rlm@8 280 pc <= pc_plus4;
rlm@8 281 end
rlm@8 282
rlm@8 283 endrule
rlm@8 284
rlm@8 285 rule discard (instRespQ.first() matches tagged LoadResp .ld
rlm@8 286 &&& ld.tag != epoch);
rlm@8 287 traceTiny("mkProc", "stage", "D");
rlm@8 288 instRespQ.deq();
rlm@8 289 endrule
rlm@8 290
rlm@8 291 (* conflict_free = "exec, writeback" *)
rlm@8 292 rule exec (instRespQ.first() matches tagged LoadResp.ld
rlm@8 293 &&& (ld.tag == epoch)
rlm@8 294 &&& unpack(ld.data) matches .inst
punk@68 295 &&& !stall(inst, wbQ)
punk@68 296 &&& !stallMTCO_MFCO(inst));
rlm@8 297
rlm@8 298 // Some abbreviations
rlm@8 299 let sext = signExtend;
rlm@8 300 let zext = zeroExtend;
rlm@8 301 let sra = signedShiftRight;
rlm@8 302
rlm@8 303 // Get the instruction
rlm@8 304
rlm@8 305 instRespQ.deq();
rlm@8 306 Instr inst
rlm@8 307 = case ( instRespQ.first() ) matches
rlm@8 308 tagged LoadResp .ld : return unpack(ld.data);
rlm@8 309 tagged StoreResp .st : return ?;
rlm@8 310 endcase;
rlm@8 311
rlm@8 312 // Get the PC info
rlm@8 313 let instrpc = pcQ.first().qpc;
rlm@8 314 let pc_plus4 = instrpc + 4;
rlm@8 315
rlm@8 316 Bool branchTaken = False;
rlm@8 317 Addr newPC = pc_plus4;
rlm@8 318
rlm@8 319 // Tracing
rlm@8 320 traceTiny("mkProc", "exec","X");
rlm@8 321 traceTiny("mkProc", "exInstTiny",inst);
rlm@8 322 traceFull("mkProc", "exInstFull",inst);
rlm@8 323
punk@68 324 // $display("PROCESSOR: Exec Fires");
rlm@8 325 case ( inst ) matches
rlm@8 326
rlm@8 327 // -- Memory Ops ------------------------------------------------
rlm@8 328
rlm@8 329 tagged LW .it :
rlm@8 330 begin
punk@63 331 let val_rbase <- rf.rd1(it.rbase);
punk@63 332 Addr addr = val_rbase + sext(it.offset);
rlm@8 333 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
rlm@8 334 wbQ.enq(tagged WB_Load it.rdst);
rlm@8 335 end
rlm@8 336
rlm@8 337 tagged SW .it :
rlm@8 338 begin
punk@63 339 let val_rbase <- rf.rd1(it.rbase);
punk@63 340 let val_rsrc2 <- rf.rd2(it.rsrc);
punk@63 341 Addr addr = val_rbase + sext(it.offset);
punk@63 342 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:val_rsrc2 } );
rlm@8 343 wbQ.enq(tagged WB_Store);
rlm@8 344 end
rlm@8 345
rlm@8 346 // -- Simple Ops ------------------------------------------------
rlm@8 347
rlm@8 348 tagged ADDIU .it :
rlm@8 349 begin
punk@63 350 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 351 Bit#(32) result = val_rsrc1 + sext(it.imm);
rlm@8 352 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
rlm@8 353 end
punk@63 354 tagged SLTI .it :
punk@63 355 begin
punk@63 356 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 357 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( val_rsrc1, sext(it.imm) )});
punk@63 358 end
punk@63 359 tagged SLTIU .it :
punk@63 360 begin
punk@63 361 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 362 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( val_rsrc1, sext(it.imm) ) });
punk@63 363 end
rlm@8 364 tagged ANDI .it :
rlm@8 365 begin
punk@63 366 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 367 Bit#(32) zext_it_imm = zext(it.imm);
punk@63 368 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 & zext_it_imm)} );
rlm@8 369 end
rlm@8 370 tagged ORI .it :
rlm@8 371 begin
punk@63 372 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 373 Bit#(32) zext_it_imm = zext(it.imm);
punk@63 374 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 | zext_it_imm)} );
rlm@8 375 end
rlm@8 376 tagged XORI .it :
rlm@8 377 begin
punk@63 378 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 379 Bit#(32) zext_it_imm = zext(it.imm);
punk@63 380 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 ^ zext_it_imm )});
rlm@8 381 end
rlm@8 382 tagged LUI .it :
rlm@8 383 begin
rlm@8 384 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 385 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
rlm@8 386 end
rlm@8 387
rlm@8 388 tagged SLL .it :
rlm@8 389 begin
punk@63 390 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 391 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@63 392 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << zext_it_shamt )} );
rlm@8 393 end
rlm@8 394 tagged SRL .it :
rlm@8 395 begin
punk@63 396 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 397 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@63 398 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> zext_it_shamt )});
rlm@8 399 end
rlm@8 400 tagged SRA .it :
rlm@8 401 begin
punk@63 402 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 403 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@63 404 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, zext_it_shamt )});
rlm@8 405 end
punk@63 406 tagged SLLV .it :
punk@63 407 begin
punk@63 408 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 409 let val_rshamt <- rf.rd2(it.rshamt);
punk@63 410 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << rshft(val_rshamt) )});
punk@63 411 end
punk@63 412 tagged SRLV .it :
punk@63 413 begin
punk@63 414 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 415 let val_rshamt <- rf.rd2(it.rshamt);
punk@63 416 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> rshft(val_rshamt) )} );
punk@63 417 end
punk@63 418 tagged SRAV .it :
punk@63 419 begin
punk@63 420 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 421 let val_rshamt <- rf.rd2(it.rshamt);
punk@63 422 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, rshft(val_rshamt) ) });
punk@63 423 end
punk@63 424 tagged ADDU .it :
punk@63 425 begin
punk@63 426 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 427 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 428 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 + val_rsrc22 )} );
punk@63 429 end
punk@63 430 tagged SUBU .it :
punk@63 431 begin
punk@63 432 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 433 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 434 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 - val_rsrc22 )} );
punk@63 435 end
punk@63 436 tagged AND .it :
punk@63 437 begin
punk@63 438 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 439 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 440 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 & val_rsrc22 )} );
punk@63 441 end
punk@63 442 tagged OR .it :
punk@63 443 begin
punk@63 444 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 445 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 446 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 | val_rsrc22 )} );
punk@63 447 end
punk@63 448 tagged XOR .it :
punk@63 449 begin
punk@63 450 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 451 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 452 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 ^ val_rsrc22 )} );
punk@63 453 end
punk@63 454 tagged NOR .it :
punk@63 455 begin
punk@63 456 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 457 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 458 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(val_rsrc11 | val_rsrc22) )} );
punk@63 459 end
punk@63 460 tagged SLT .it :
punk@63 461 begin
punk@63 462 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 463 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 464 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( val_rsrc11, val_rsrc22 ) });
punk@63 465 end
punk@63 466 tagged SLTU .it :
punk@63 467 begin
punk@63 468 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 469 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 470 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( val_rsrc11, val_rsrc22 ) });
punk@63 471 end
rlm@8 472
rlm@8 473 // -- Branches --------------------------------------------------
rlm@8 474
rlm@8 475 tagged BLEZ .it :
punk@63 476 begin
punk@63 477 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 478 if ( signedLE( val_rsrc1, 0 ) )
punk@63 479 begin
rlm@8 480 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 481 branchTaken = True;
punk@63 482 end
punk@63 483 end
rlm@8 484
rlm@8 485 tagged BGTZ .it :
punk@63 486 begin
punk@63 487 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 488 if ( signedGT( val_rsrc1, 0 ) )
rlm@8 489 begin
rlm@8 490 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 491 branchTaken = True;
rlm@8 492 end
punk@63 493 end
rlm@8 494
rlm@8 495 tagged BLTZ .it :
punk@63 496 begin
punk@63 497 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 498 if ( signedLT( val_rsrc1, 0 ) )
rlm@8 499 begin
rlm@8 500 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 501 branchTaken = True;
rlm@8 502 end
punk@63 503 end
rlm@8 504
punk@63 505 tagged BGEZ .it :
punk@63 506 begin
punk@63 507 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 508 if ( signedGE( val_rsrc1, 0 ) )
punk@63 509 begin
punk@63 510 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@63 511 branchTaken = True;
punk@63 512 end
punk@63 513 end
rlm@8 514
rlm@8 515 tagged BEQ .it :
punk@63 516 begin
punk@63 517 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 518 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 519 if ( val_rsrc11 == val_rsrc22 )
rlm@8 520 begin
rlm@8 521 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 522 branchTaken = True;
rlm@8 523 end
punk@63 524 end
rlm@8 525
rlm@8 526 tagged BNE .it :
punk@63 527 begin
punk@63 528 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 529 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 530 if ( val_rsrc11 != val_rsrc22 )
rlm@8 531 begin
rlm@8 532 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 533 branchTaken = True;
rlm@8 534 end
punk@63 535 end
rlm@8 536
rlm@8 537 // -- Jumps -----------------------------------------------------
rlm@8 538
rlm@8 539 tagged J .it :
punk@63 540 begin
rlm@8 541 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8 542 branchTaken = True;
rlm@8 543 end
rlm@8 544
rlm@8 545 tagged JR .it :
punk@42 546 begin
punk@63 547 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 548 newPC = val_rsrc1;
rlm@8 549 branchTaken = True;
rlm@8 550 end
rlm@8 551
rlm@8 552 tagged JAL .it :
rlm@8 553 begin
rlm@8 554 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
rlm@8 555 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8 556 branchTaken = True;
rlm@8 557 end
rlm@8 558
rlm@8 559 tagged JALR .it :
rlm@8 560 begin
punk@63 561 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 562 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
punk@63 563 newPC = val_rsrc1;
rlm@8 564 branchTaken = True;
rlm@8 565 end
rlm@8 566
rlm@8 567 // -- Cop0 ------------------------------------------------------
rlm@8 568
punk@33 569 tagged MTC0 .it : //Recieve things from host computer
rlm@8 570 begin
punk@63 571 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@43 572 // $display( " PROCESSOR MTC0 call\n");
rlm@8 573 case ( it.cop0dst )
punk@63 574 5'd10 : cp0_statsEn <= unpack(truncate(val_rsrc1));
punk@63 575 5'd21 : cp0_tohost <= truncate(val_rsrc1);
punk@63 576 5'd26 : cp0_progComp <= unpack(truncate(val_rsrc1)); //states audio program completed and termination okay
punk@68 577 5'd27 : outAudioFifo.enq(AudioStream {voice: channel, data: tagged Valid
punk@68 578 tagged Sample unpack(truncate(val_rsrc1)) }); //Bit size is 16 not 32
rlm@8 579 default :
rlm@8 580 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
rlm@8 581 endcase
rlm@8 582 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
rlm@8 583 end
rlm@8 584
rlm@8 585 //this is host stuff?
punk@33 586 tagged MFC0 .it : //Things out
rlm@8 587 begin
rlm@8 588 case ( it.cop0src )
rlm@8 589 // not actually an ALU instruction but don't have the format otherwise
rlm@8 590 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
rlm@8 591 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
rlm@8 592 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
punk@33 593 5'd25 : begin
punk@68 594 // $display( "**** EOF Requested\n "); //Should never run if inAudioFifo.first not valid
punk@68 595 let stream = inAudioFifo.first();
punk@68 596 if (stream.data matches tagged Valid .sample)
punk@68 597 begin
punk@68 598 case (sample) matches
punk@68 599 tagged EndOfFile :
punk@68 600 begin
punk@68 601 $display("PROCESSOR sent toC EOF");
punk@68 602 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(True)) }); // Reading clears bit
punk@68 603 inAudioFifo.deq;
punk@68 604 end
punk@68 605 tagged Sample .audio:
punk@68 606 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(False)) }); // Reading clears bit
punk@68 607 endcase
punk@68 608 code_bypass <= False;
punk@68 609 end
punk@68 610 else $display("PROCESSOR code trying to read Invalid Audio Stream");
punk@33 611 end
punk@33 612 5'd28 : begin
punk@65 613 $display( "***** Reqesting Sample");
punk@68 614 let stream = inAudioFifo.first(); // is this going to cause perf. delay?
punk@68 615 if (stream.data matches tagged Valid .sample)
punk@68 616 begin
punk@68 617 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
punk@68 618 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
punk@68 619 else $display ( "Audio File EOF Reached. Invalid sample request.");
punk@68 620 inAudioFifo.deq();
punk@68 621 end
punk@68 622 else $display("PROCESSOR code trying to read Invalid Audio Stream");
punk@33 623 end
rlm@8 624 default :
rlm@8 625 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
rlm@8 626 endcase
rlm@8 627 end
rlm@8 628
rlm@8 629 // -- Illegal ---------------------------------------------------
rlm@8 630
rlm@8 631 default :
rlm@8 632 $display( " RTL-ERROR : %m : Illegal instruction !" );
rlm@8 633
rlm@8 634 endcase
rlm@8 635
rlm@8 636 //evaluate branch prediction
rlm@8 637 Addr ppc = pcQ.first().qnxtpc; //predicted branch
rlm@8 638 if (ppc != newPC) //prediction wrong
rlm@8 639 begin
rlm@8 640 epoch <= pcQ.first().qepoch + 1;
rlm@8 641 bp.upd(instrpc, newPC); //update branch predictor
rlm@8 642 pcQ.clear();
rlm@8 643 pc <= newPC;
rlm@8 644 end
rlm@8 645 else
rlm@8 646 pcQ.deq();
rlm@49 647 //rlm: removing
rlm@49 648 // if ( cp0_statsEn )
rlm@49 649 // num_inst.incr();
rlm@8 650
rlm@8 651 endrule
rlm@8 652
rlm@8 653 rule writeback; // ( stage == Writeback );
rlm@8 654 traceTiny("mkProc", "writeback","W");
rlm@8 655
rlm@8 656
rlm@8 657 // get what to do off the writeback queue
rlm@8 658 wbQ.deq();
rlm@8 659 case (wbQ.first()) matches
rlm@8 660 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
rlm@8 661 tagged WB_Load .regWr :
rlm@8 662 begin
rlm@8 663 dataRespQ.deq();
rlm@8 664 if (dataRespQ.first() matches tagged LoadResp .ld)
rlm@8 665 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
rlm@8 666 end
rlm@8 667 tagged WB_Store : dataRespQ.deq();
rlm@8 668 tagged WB_Host .dat : noAction;
rlm@8 669 endcase
rlm@8 670
rlm@8 671 endrule
rlm@8 672
rlm@49 673 //rlm remove
rlm@49 674 // rule inc_num_cycles;
rlm@49 675 // if ( cp0_statsEn )
rlm@49 676 // num_cycles.incr();
rlm@49 677 // endrule
punk@11 678
punk@68 679 rule bypass (code_bypass &&&
punk@68 680 !cp0_progComp &&& //never fires at the same time as sendEnd where it is enabled
punk@68 681 inAudioFifo.first().data matches tagged Invalid) ;
punk@43 682 outAudioFifo.enq(inAudioFifo.first());
punk@43 683 inAudioFifo.deq;
punk@43 684 endrule
punk@68 685
punk@50 686 /*
punk@33 687 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
punk@37 688 $display (" PROCESSOR End Audio Flag Set ");
punk@33 689 cp0_audioEOF <= True;
punk@33 690 inAudioFifo.deq;
punk@33 691 endrule
punk@50 692 */
punk@68 693 (* descending_urgency = "sendProcEnd, exec" *)
punk@50 694 rule sendProcEnd (cp0_progComp);
punk@33 695 $display (" PROCESSOR Says Program Complete ");
punk@68 696 outAudioFifo.enq(AudioStream {voice: channel, data: tagged Valid tagged EndOfFile }); // Only send one
punk@68 697 cp0_progComp <= False; // And functions to reset
punk@68 698 code_bypass <= True; // Enable Bypass so that invalids get thru
punk@11 699 endrule
punk@43 700
punk@12 701
rlm@8 702 //-----------------------------------------------------------
rlm@8 703 // Methods
rlm@8 704
rlm@8 705 interface Client imem_client;
punk@21 706 interface Get request = fifoToGet(instReqQ);
punk@21 707 interface Put response = fifoToPut(instRespQ);
rlm@8 708 endinterface
rlm@8 709
rlm@8 710 interface Client dmem_client;
punk@21 711 interface Get request = fifoToGet(dataReqQ);
punk@21 712 interface Put response = fifoToPut(dataRespQ);
rlm@8 713 endinterface
rlm@8 714
rlm@8 715 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
rlm@8 716
punk@36 717 /*
punk@36 718 interface CPUToHost tohost;
punk@36 719 method Bit#(32) cpuToHost(int req);
punk@36 720 return (case (req)
punk@36 721 0: cp0_tohost;
punk@36 722 1: pc;
punk@36 723 2: zeroExtend(pack(stage));
punk@36 724 endcase);
punk@36 725 endmethod
punk@36 726 endinterface
punk@36 727 */
punk@36 728
punk@21 729 interface Get sampleOutput = fifoToGet(outAudioFifo);
punk@36 730 interface Put sampleInput = fifoToPut(inAudioFifo);
punk@68 731 interface Get pcCount = toGet(asReg(pc));
punk@11 732
rlm@8 733 endmodule
rlm@8 734