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annotate modules/bluespec/Pygar/core/Processor.bsv @ 16:7e1510b47336 pygar svn.17

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[svn r17] added rest of items for core
author punk
date Tue, 27 Apr 2010 22:54:50 -0400
parents a1833d9f6e3d
children 9910c032f38d
rev   line source
rlm@8 1 /// The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@8 23 import Connectable::*;
rlm@8 24 import GetPut::*;
rlm@8 25 import ClientServer::*;
rlm@8 26 import RegFile::*;
rlm@8 27
rlm@8 28 import FIFO::*;
rlm@8 29 import FIFOF::*;
rlm@8 30 import SFIFO::*;
rlm@8 31 import RWire::*;
rlm@8 32
punk@11 33 import Trace::*;
rlm@8 34 import BFIFO::*;
rlm@8 35 import MemTypes::*;
rlm@8 36 import ProcTypes::*;
rlm@8 37 import BRegFile::*;
rlm@8 38 import BranchPred::*;
rlm@8 39 //import PathTypes::*; This is only there to force the debugging
rlm@8 40
rlm@8 41 //AWB includes
rlm@8 42 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8 43 `include "asim/provides/soft_connections.bsh"
rlm@8 44 `include "asim/provides/common_services.bsh"
rlm@8 45
rlm@8 46 // Local includes
punk@11 47 //`include "asim/provides/processor_library.bsh" (included above directly)
punk@12 48 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
rlm@8 49 `include "asim/provides/common_services.bsh"
rlm@8 50 `include "asim/dict/STATS_PROCESSOR.bsh"
rlm@8 51
punk@11 52 // Local includes. Look for the correspondingly named .awb files
punk@11 53 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@11 54 // to find the actual Bluespec files which are used to generate
punk@11 55 // these includes. These files are specific to this audio processing
punk@11 56 // pipeline
punk@11 57
punk@12 58 `include "asim/provides/audio_pipe_types.bsh"
rlm@8 59
punk@12 60 //interface CPUToHost;
punk@12 61 // method Bit#(32) cpuToHost(int req);
punk@12 62 //endinterface
rlm@8 63
rlm@8 64 interface Proc;
rlm@8 65
rlm@8 66 // Interface from processor to caches
rlm@8 67 interface Client#(DataReq,DataResp) dmem_client;
rlm@8 68 interface Client#(InstReq,InstResp) imem_client;
rlm@8 69
rlm@8 70 // Interface for enabling/disabling statistics on the rest of the core
rlm@8 71 interface Get#(Bool) statsEn_get;
rlm@8 72
punk@12 73 // // Interface to host
punk@12 74 // interface CPUToHost tohost;
rlm@8 75
punk@11 76 // Interface to Audio Pipeline
punk@15 77 interface Get#(AudioProcessorUnit) sampleOutput;
punk@11 78
rlm@8 79 endinterface
rlm@8 80
punk@11 81 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
punk@15 82 //interface AudioOut;
punk@15 83 // interface Get#(AudioProcessorUnit) audioSampleOutput;
punk@15 84 //endinterface
rlm@8 85
punk@12 86 //interface AudioIn;
punk@12 87 // interface Put#(AudioProcessorUnit) audioSampleInput;
punk@12 88 //endinterface
punk@12 89
rlm@8 90 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
rlm@8 91
rlm@8 92 //-----------------------------------------------------------
rlm@8 93 // Register file module
rlm@8 94 //-----------------------------------------------------------
rlm@8 95
rlm@8 96 interface BRFile;
rlm@8 97 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8 98 method Bit#(32) rd1( Rindx rindx );
rlm@8 99 method Bit#(32) rd2( Rindx rindx );
rlm@8 100 endinterface
rlm@8 101
rlm@8 102 module mkBRFile( BRFile );
rlm@8 103
rlm@8 104 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
rlm@8 105
rlm@8 106 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8 107 rfile.upd( rindx, data );
rlm@8 108 endmethod
rlm@8 109
rlm@8 110 method Bit#(32) rd1( Rindx rindx );
rlm@8 111 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8 112 endmethod
rlm@8 113
rlm@8 114 method Bit#(32) rd2( Rindx rindx );
rlm@8 115 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8 116 endmethod
rlm@8 117
rlm@8 118 endmodule
rlm@8 119
rlm@8 120 //-----------------------------------------------------------
rlm@8 121 // Helper functions
rlm@8 122 //-----------------------------------------------------------
rlm@8 123
rlm@8 124 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
rlm@8 125 return zeroExtend( pack( signedLT(val1,val2) ) );
rlm@8 126 endfunction
rlm@8 127
rlm@8 128 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
rlm@8 129 return zeroExtend( pack( val1 < val2 ) );
rlm@8 130 endfunction
rlm@8 131
rlm@8 132 function Bit#(32) rshft( Bit#(32) val );
rlm@8 133 return zeroExtend(val[4:0]);
rlm@8 134 endfunction
rlm@8 135
rlm@8 136
rlm@8 137 //-----------------------------------------------------------
rlm@8 138 // Find funct for wbQ
rlm@8 139 //-----------------------------------------------------------
rlm@8 140 function Bool findwbf(Rindx fVal, WBResult cmpVal);
rlm@8 141 case (cmpVal) matches
rlm@8 142 tagged WB_ALU {data:.res, dest:.rd} :
rlm@8 143 return (fVal == rd);
rlm@8 144 tagged WB_Load .rd :
rlm@8 145 return (fVal == rd);
rlm@8 146 tagged WB_Store .st :
rlm@8 147 return False;
rlm@8 148 tagged WB_Host .x :
rlm@8 149 return False;
rlm@8 150 endcase
rlm@8 151 endfunction
rlm@8 152
rlm@8 153
rlm@8 154 //-----------------------------------------------------------
rlm@8 155 // Stall funct for wbQ
rlm@8 156 //-----------------------------------------------------------
rlm@8 157 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
rlm@8 158 case (inst) matches
rlm@8 159 // -- Memory Ops ------------------------------------------------
rlm@8 160 tagged LW .it :
rlm@8 161 return f.find(it.rbase);
rlm@8 162 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
rlm@8 163 return (f.find(addr) || f.find2(dreg));
rlm@8 164
rlm@8 165 // -- Simple Ops ------------------------------------------------
rlm@8 166 tagged ADDIU .it : return f.find(it.rsrc);
rlm@8 167 tagged SLTI .it : return f.find(it.rsrc);
rlm@8 168 tagged SLTIU .it : return f.find(it.rsrc);
rlm@8 169 tagged ANDI .it : return f.find(it.rsrc);
rlm@8 170 tagged ORI .it : return f.find(it.rsrc);
rlm@8 171 tagged XORI .it : return f.find(it.rsrc);
rlm@8 172
rlm@8 173 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
rlm@8 174 tagged SLL .it : return f.find(it.rsrc);
rlm@8 175 tagged SRL .it : return f.find(it.rsrc);
rlm@8 176 tagged SRA .it : return f.find(it.rsrc);
rlm@8 177 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 178 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 179 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 180 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 181 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 182 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 183 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 184 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 185 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 186 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 187 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 188
rlm@8 189
rlm@8 190 // -- Branches --------------------------------------------------
rlm@8 191
rlm@8 192 tagged BLEZ .it : return (f.find(it.rsrc));
rlm@8 193 tagged BGTZ .it : return (f.find(it.rsrc));
rlm@8 194 tagged BLTZ .it : return (f.find(it.rsrc));
rlm@8 195 tagged BGEZ .it : return (f.find(it.rsrc));
rlm@8 196 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 197 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 198
rlm@8 199 // -- Jumps -----------------------------------------------------
rlm@8 200
rlm@8 201 tagged J .it : return False;
rlm@8 202 tagged JR .it : return f.find(it.rsrc);
rlm@8 203 tagged JALR .it : return f.find(it.rsrc);
rlm@8 204 tagged JAL .it : return False;
rlm@8 205
rlm@8 206 // -- Cop0 ------------------------------------------------------
rlm@8 207
rlm@8 208 tagged MTC0 .it : return f.find(it.rsrc);
rlm@8 209 tagged MFC0 .it : return False;
rlm@8 210
rlm@8 211 // -- Illegal ---------------------------------------------------
rlm@8 212
rlm@8 213 default : return False;
rlm@8 214
rlm@8 215 endcase
rlm@8 216 endfunction
rlm@8 217 //-----------------------------------------------------------
rlm@8 218 // Reference processor
rlm@8 219 //-----------------------------------------------------------
rlm@8 220
rlm@8 221
rlm@8 222 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
rlm@8 223 //(* synthesize *)
rlm@8 224
rlm@8 225 module [CONNECTED_MODULE] mkProc( Proc );
rlm@8 226
rlm@8 227 //-----------------------------------------------------------
rlm@8 228 // Debug port
rlm@8 229
punk@12 230 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
rlm@8 231
rlm@8 232
rlm@8 233 //-----------------------------------------------------------
rlm@8 234 // State
rlm@8 235
rlm@8 236 // Standard processor state
rlm@8 237
rlm@8 238 Reg#(Addr) pc <- mkReg(32'h00001000);
rlm@8 239 Reg#(Epoch) epoch <- mkReg(0);
rlm@8 240 Reg#(Stage) stage <- mkReg(PCgen);
rlm@8 241 BRFile rf <- mkBRFile;
rlm@8 242
rlm@8 243 // Branch Prediction
rlm@8 244 BranchPred bp <- mkBranchPred();
rlm@8 245 FIFO#(PCStat) execpc <- mkLFIFO();
rlm@8 246
rlm@8 247 // Pipelines
rlm@8 248 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
rlm@8 249 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
rlm@8 250
rlm@8 251 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
rlm@8 252 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
rlm@8 253 Reg#(Bool) cp0_statsEn <- mkReg(False);
rlm@8 254
rlm@8 255 // Memory request/response state
rlm@8 256
rlm@8 257 FIFO#(InstReq) instReqQ <- mkBFIFO1();
rlm@8 258 FIFO#(InstResp) instRespQ <- mkFIFO();
rlm@8 259
rlm@8 260 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
rlm@8 261 FIFO#(DataResp) dataRespQ <- mkFIFO();
rlm@8 262
punk@11 263 // Audio I/O
punk@11 264 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
punk@11 265 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
punk@11 266
punk@11 267
punk@11 268 // Statistics state (2010)
punk@11 269 // Reg#(Stat) num_cycles <- mkReg(0);
punk@11 270 // Reg#(Stat) num_inst <- mkReg(0);
rlm@8 271
rlm@8 272 //Or:
punk@11 273 // Statistics state
punk@11 274 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
punk@11 275 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
rlm@8 276
rlm@8 277 //-----------------------------------------------------------
rlm@8 278 // Rules
rlm@8 279
rlm@8 280 (* descending_urgency = "exec, pcgen" *)
rlm@8 281 rule pcgen; //( stage == PCgen );
rlm@8 282 let pc_plus4 = pc + 4;
rlm@8 283
rlm@8 284 traceTiny("mkProc", "pc",pc);
rlm@8 285 traceTiny("mkProc", "pcgen","P");
rlm@8 286 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
rlm@8 287
rlm@8 288 let next_pc = bp.get(pc);
rlm@8 289 if (next_pc matches tagged Valid .npc)
rlm@8 290 begin
rlm@8 291 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
rlm@8 292 pc <= npc;
rlm@8 293 end
rlm@8 294 else
rlm@8 295 begin
rlm@8 296 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
rlm@8 297 pc <= pc_plus4;
rlm@8 298 end
rlm@8 299
rlm@8 300 endrule
rlm@8 301
rlm@8 302 rule discard (instRespQ.first() matches tagged LoadResp .ld
rlm@8 303 &&& ld.tag != epoch);
rlm@8 304 traceTiny("mkProc", "stage", "D");
rlm@8 305 instRespQ.deq();
rlm@8 306 endrule
rlm@8 307
rlm@8 308 (* conflict_free = "exec, writeback" *)
rlm@8 309 rule exec (instRespQ.first() matches tagged LoadResp.ld
rlm@8 310 &&& (ld.tag == epoch)
rlm@8 311 &&& unpack(ld.data) matches .inst
rlm@8 312 &&& !stall(inst, wbQ));
rlm@8 313
rlm@8 314 // Some abbreviations
rlm@8 315 let sext = signExtend;
rlm@8 316 let zext = zeroExtend;
rlm@8 317 let sra = signedShiftRight;
rlm@8 318
rlm@8 319 // Get the instruction
rlm@8 320
rlm@8 321 instRespQ.deq();
rlm@8 322 Instr inst
rlm@8 323 = case ( instRespQ.first() ) matches
rlm@8 324 tagged LoadResp .ld : return unpack(ld.data);
rlm@8 325 tagged StoreResp .st : return ?;
rlm@8 326 endcase;
rlm@8 327
rlm@8 328 // Get the PC info
rlm@8 329 let instrpc = pcQ.first().qpc;
rlm@8 330 let pc_plus4 = instrpc + 4;
rlm@8 331
rlm@8 332 Bool branchTaken = False;
rlm@8 333 Addr newPC = pc_plus4;
rlm@8 334
rlm@8 335 // Tracing
rlm@8 336 traceTiny("mkProc", "exec","X");
rlm@8 337 traceTiny("mkProc", "exInstTiny",inst);
rlm@8 338 traceFull("mkProc", "exInstFull",inst);
rlm@8 339
rlm@8 340 case ( inst ) matches
rlm@8 341
rlm@8 342 // -- Memory Ops ------------------------------------------------
rlm@8 343
rlm@8 344 tagged LW .it :
rlm@8 345 begin
rlm@8 346 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8 347 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
rlm@8 348 wbQ.enq(tagged WB_Load it.rdst);
rlm@8 349 end
rlm@8 350
rlm@8 351 tagged SW .it :
rlm@8 352 begin
rlm@8 353 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8 354 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
rlm@8 355 wbQ.enq(tagged WB_Store);
rlm@8 356 end
rlm@8 357
rlm@8 358 // -- Simple Ops ------------------------------------------------
rlm@8 359
rlm@8 360 tagged ADDIU .it :
rlm@8 361 begin
rlm@8 362 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
rlm@8 363 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
rlm@8 364 end
rlm@8 365 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
rlm@8 366 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
rlm@8 367 tagged ANDI .it :
rlm@8 368 begin
rlm@8 369 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 370 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
rlm@8 371 end
rlm@8 372 tagged ORI .it :
rlm@8 373 begin
rlm@8 374 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 375 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
rlm@8 376 end
rlm@8 377 tagged XORI .it :
rlm@8 378 begin
rlm@8 379 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 380 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
rlm@8 381 end
rlm@8 382 tagged LUI .it :
rlm@8 383 begin
rlm@8 384 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 385 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
rlm@8 386 end
rlm@8 387
rlm@8 388 tagged SLL .it :
rlm@8 389 begin
rlm@8 390 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8 391 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
rlm@8 392 end
rlm@8 393 tagged SRL .it :
rlm@8 394 begin
rlm@8 395 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8 396 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
rlm@8 397 end
rlm@8 398 tagged SRA .it :
rlm@8 399 begin
rlm@8 400 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8 401 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
rlm@8 402 end
rlm@8 403 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
rlm@8 404 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
rlm@8 405 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
rlm@8 406 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
rlm@8 407 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
rlm@8 408 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
rlm@8 409 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
rlm@8 410 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
rlm@8 411 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
rlm@8 412 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8 413 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8 414
rlm@8 415 // -- Branches --------------------------------------------------
rlm@8 416
rlm@8 417 tagged BLEZ .it :
rlm@8 418 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
rlm@8 419 begin
rlm@8 420 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 421 branchTaken = True;
rlm@8 422 end
rlm@8 423
rlm@8 424 tagged BGTZ .it :
rlm@8 425 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
rlm@8 426 begin
rlm@8 427 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 428 branchTaken = True;
rlm@8 429 end
rlm@8 430
rlm@8 431 tagged BLTZ .it :
rlm@8 432 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
rlm@8 433 begin
rlm@8 434 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 435 branchTaken = True;
rlm@8 436 end
rlm@8 437
rlm@8 438 tagged BGEZ .it :
rlm@8 439 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
rlm@8 440 begin
rlm@8 441 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 442 branchTaken = True;
rlm@8 443 end
rlm@8 444
rlm@8 445 tagged BEQ .it :
rlm@8 446 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
rlm@8 447 begin
rlm@8 448 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 449 branchTaken = True;
rlm@8 450 end
rlm@8 451
rlm@8 452 tagged BNE .it :
rlm@8 453 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
rlm@8 454 begin
rlm@8 455 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 456 branchTaken = True;
rlm@8 457 end
rlm@8 458
rlm@8 459 // -- Jumps -----------------------------------------------------
rlm@8 460
rlm@8 461 tagged J .it :
rlm@8 462 begin
rlm@8 463 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8 464 branchTaken = True;
rlm@8 465 end
rlm@8 466
rlm@8 467 tagged JR .it :
rlm@8 468 begin
rlm@8 469 newPC = rf.rd1(it.rsrc);
rlm@8 470 branchTaken = True;
rlm@8 471 end
rlm@8 472
rlm@8 473 tagged JAL .it :
rlm@8 474 begin
rlm@8 475 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
rlm@8 476 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8 477 branchTaken = True;
rlm@8 478 end
rlm@8 479
rlm@8 480 tagged JALR .it :
rlm@8 481 begin
rlm@8 482 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
rlm@8 483 newPC = rf.rd1(it.rsrc);
rlm@8 484 branchTaken = True;
rlm@8 485 end
rlm@8 486
rlm@8 487 // -- Cop0 ------------------------------------------------------
rlm@8 488
rlm@8 489 tagged MTC0 .it :
rlm@8 490 begin
rlm@8 491 case ( it.cop0dst )
rlm@8 492 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
rlm@8 493 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
rlm@8 494 default :
rlm@8 495 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
rlm@8 496 endcase
rlm@8 497 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
rlm@8 498 end
rlm@8 499
rlm@8 500 //this is host stuff?
rlm@8 501 tagged MFC0 .it :
rlm@8 502 begin
rlm@8 503 case ( it.cop0src )
rlm@8 504 // not actually an ALU instruction but don't have the format otherwise
rlm@8 505 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
rlm@8 506 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
rlm@8 507 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
rlm@8 508 default :
rlm@8 509 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
rlm@8 510 endcase
rlm@8 511 end
rlm@8 512
rlm@8 513 // -- Illegal ---------------------------------------------------
rlm@8 514
rlm@8 515 default :
rlm@8 516 $display( " RTL-ERROR : %m : Illegal instruction !" );
rlm@8 517
rlm@8 518 endcase
rlm@8 519
rlm@8 520 //evaluate branch prediction
rlm@8 521 Addr ppc = pcQ.first().qnxtpc; //predicted branch
rlm@8 522 if (ppc != newPC) //prediction wrong
rlm@8 523 begin
rlm@8 524 epoch <= pcQ.first().qepoch + 1;
rlm@8 525 bp.upd(instrpc, newPC); //update branch predictor
rlm@8 526 pcQ.clear();
rlm@8 527 pc <= newPC;
rlm@8 528 end
rlm@8 529 else
rlm@8 530 pcQ.deq();
rlm@8 531
rlm@8 532 if ( cp0_statsEn )
punk@11 533 num_inst.incr();
rlm@8 534
rlm@8 535 endrule
rlm@8 536
rlm@8 537 rule writeback; // ( stage == Writeback );
rlm@8 538 traceTiny("mkProc", "writeback","W");
rlm@8 539
rlm@8 540
rlm@8 541 // get what to do off the writeback queue
rlm@8 542 wbQ.deq();
rlm@8 543 case (wbQ.first()) matches
rlm@8 544 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
rlm@8 545 tagged WB_Load .regWr :
rlm@8 546 begin
rlm@8 547 dataRespQ.deq();
rlm@8 548 if (dataRespQ.first() matches tagged LoadResp .ld)
rlm@8 549 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
rlm@8 550 end
rlm@8 551 tagged WB_Store : dataRespQ.deq();
rlm@8 552 tagged WB_Host .dat : noAction;
rlm@8 553 endcase
rlm@8 554
rlm@8 555 endrule
rlm@8 556
rlm@8 557 rule inc_num_cycles;
rlm@8 558 if ( cp0_statsEn )
punk@11 559 num_cycles.incr();
rlm@8 560 endrule
punk@11 561
punk@11 562 (* conservative_implicit_conditions *)
punk@11 563 rule handleCPUToHost;
punk@11 564 let req <- server_stub.acceptRequest_ReadCPUToHost();
punk@11 565 case (req)
punk@15 566 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
punk@11 567 1: server_stub.sendResponse_ReadCPUToHost(pc);
punk@11 568 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
punk@11 569 endcase
punk@11 570 endrule
punk@11 571
punk@11 572 // for now, we don't do anything.
punk@11 573 rule connectAudioReqResp;
punk@11 574 $display("FIR copies a data");
punk@11 575 outAudioFifo.enq(inAudioFifo.first);
punk@11 576 outAudioFifo.deq;
punk@11 577 endrule
rlm@8 578
punk@12 579 // Server items & rules:
punk@12 580
punk@12 581 rule feedInput;
punk@12 582 let command <- server_stub.acceptRequest_SendUnprocessedStream();
punk@12 583 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
punk@12 584
punk@12 585 if(ctrl == EndOfFile)
punk@12 586 begin
punk@12 587 inAudioFifo.enq(tagged EndOfFile);
punk@12 588 end
punk@12 589 else
punk@12 590 begin
punk@12 591 inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
punk@12 592 end
punk@12 593 endrule
punk@12 594
punk@12 595
rlm@8 596 //-----------------------------------------------------------
rlm@8 597 // Methods
rlm@8 598
rlm@8 599 interface Client imem_client;
rlm@8 600 interface Get request = toGet(instReqQ);
rlm@8 601 interface Put response = toPut(instRespQ);
rlm@8 602 endinterface
rlm@8 603
rlm@8 604 interface Client dmem_client;
rlm@8 605 interface Get request = toGet(dataReqQ);
rlm@8 606 interface Put response = toPut(dataRespQ);
rlm@8 607 endinterface
rlm@8 608
rlm@8 609 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
rlm@8 610
punk@12 611 // interface CPUToHost tohost;
punk@12 612 // method Bit#(32) cpuToHost(int req);
punk@12 613 // return (case (req)
punk@12 614 // 0: cp0_tohost;
punk@12 615 // 1: pc;
punk@12 616 // 2: zeroExtend(pack(stage));
punk@12 617 // endcase);
punk@12 618 // endmethod
punk@12 619 // endinterface
punk@12 620
punk@15 621 interface Get sampleOutput;
punk@15 622 interface sampleOutput = fifoToGet(outAudioFifo);
punk@11 623 endinterface
punk@11 624
punk@11 625
rlm@8 626 endmodule
rlm@8 627