annotate modules/bluespec/Pygar/core/Core.bsv @ 16:7e1510b47336 pygar svn.17

[svn r17] added rest of items for core
author punk
date Tue, 27 Apr 2010 22:54:50 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 // The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@8 23 import Connectable::*;
rlm@8 24 import GetPut::*;
rlm@8 25 import ClientServer::*;
rlm@8 26
rlm@8 27 import DataCacheBlocking::*;
rlm@8 28 import InstCacheBlocking::*;
rlm@8 29 import Processor::*;
rlm@8 30 import MemArb::*;
rlm@8 31 import MemTypes::*;
rlm@8 32
rlm@8 33 interface CoreStats;
rlm@8 34 interface DCacheStats dcache;
rlm@8 35 interface ICacheStats icache;
rlm@8 36 interface ProcStats proc;
rlm@8 37 endinterface
rlm@8 38
rlm@8 39 interface Core;
rlm@8 40
rlm@8 41 // Interface from core to main memory
rlm@8 42 interface Client#(MainMemReq,MainMemResp) mmem_client;
rlm@8 43
rlm@8 44 // Statistics
rlm@8 45 interface CoreStats stats;
rlm@8 46
rlm@8 47 // CPU to Host
rlm@8 48 interface CPUToHost tohost;
rlm@8 49
rlm@8 50 endinterface
rlm@8 51
rlm@8 52 (* synthesize *)
rlm@8 53 module mkCore(Core);
rlm@8 54
rlm@8 55 // Instantiate the modules
rlm@8 56 Proc proc <- mkProc();
rlm@8 57 ICache#(InstReq,InstResp) icache <- mkInstCache();
rlm@8 58 DCache#(DataReq,DataResp) dcache <- mkDataCache();
rlm@8 59 MemArb marb <- mkMemArb();
rlm@8 60
rlm@8 61 // Internal connections
rlm@8 62 mkConnection( proc.statsEn_get, icache.statsEn_put );
rlm@8 63 mkConnection( proc.statsEn_get, dcache.statsEn_put );
rlm@8 64 mkConnection( proc.imem_client, icache.proc_server );
rlm@8 65 mkConnection( proc.dmem_client, dcache.proc_server );
rlm@8 66 mkConnection( icache.mmem_client, marb.cache0_server );
rlm@8 67 mkConnection( dcache.mmem_client, marb.cache1_server );
rlm@8 68
rlm@8 69 // Methods
rlm@8 70 interface mmem_client = marb.mmem_client;
rlm@8 71
rlm@8 72 interface CoreStats stats;
rlm@8 73 interface dcache = dcache.stats;
rlm@8 74 interface icache = icache.stats;
rlm@8 75 interface proc = proc.stats;
rlm@8 76 endinterface
rlm@8 77
rlm@8 78 interface CPUToHost tohost = proc.tohost;
rlm@8 79
rlm@8 80 endmodule
rlm@8 81