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1 // The MIT License
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2
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3 // Copyright (c) 2009 Massachusetts Institute of Technology
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4
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5 // Permission is hereby granted, free of charge, to any person obtaining a copy
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6 // of this software and associated documentation files (the "Software"), to deal
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7 // in the Software without restriction, including without limitation the rights
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8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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9 // copies of the Software, and to permit persons to whom the Software is
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10 // furnished to do so, subject to the following conditions:
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11
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12 // The above copyright notice and this permission notice shall be included in
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13 // all copies or substantial portions of the Software.
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14
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15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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21 // THE SOFTWARE.
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22
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23 import Connectable::*;
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24 import GetPut::*;
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25 import ClientServer::*;
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26 import FIFOF::*;
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27 import FIFO::*;
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punk@28
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28 import Trace::*;
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29
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30 // Local includes
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31 `include "asim/provides/processor_library.bsh"
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32
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33 interface MemArb;
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34
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35 interface Server#(MainMemReq,MainMemResp) cache0_server;
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36 interface Server#(MainMemReq,MainMemResp) cache1_server;
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37 interface Client#(MainMemReq,MainMemResp) mmem_client;
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38
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39 endinterface
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40
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41 typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits);
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42
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43 module mkMemArb( MemArb );
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44
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45 //-----------------------------------------------------------
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46 // State
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47
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48 FIFOF#(MainMemReq) req0Q <- mkBFIFOF1();
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49 FIFO#(MainMemResp) resp0Q <- mkBFIFO1();
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50
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51 FIFOF#(MainMemReq) req1Q <- mkBFIFOF1();
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52 FIFO#(MainMemResp) resp1Q <- mkBFIFO1();
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53
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54 FIFO#(MainMemReq) mreqQ <- mkBFIFO1();
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55 FIFO#(MainMemResp) mrespQ <- mkBFIFO1();
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56
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57 Reg#(ReqPtr) nextReq <- mkReg(REQ0);
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58
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59 //-----------------------------------------------------------
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60 // Some wires
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61
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62 let req0avail = req0Q.notEmpty();
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63 let req1avail = req1Q.notEmpty();
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64
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65 //-----------------------------------------------------------
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66 // Rules
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67
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68 rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) );
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69 traceTiny("mkMemArb", "memArb req0",req0Q.first());
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70
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71 // Rewrite tag field if this is a load ...
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72 MainMemReq mreq
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73 = case ( req0Q.first() ) matches
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74 tagged LoadReq .ld : return LoadReq { tag:0, addr:ld.addr };
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75 tagged StoreReq .st : return req0Q.first();
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76 endcase;
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77
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78 // Send out the request
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79 mreqQ.enq(mreq);
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80 nextReq <= REQ1;
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81 req0Q.deq();
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82
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83 endrule
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84
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85 rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) );
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86 traceTiny("mkMemArb", "memArb req1",req1Q.first);
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87
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88 // Rewrite tag field if this is a load ...
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89 MainMemReq mreq
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90 = case ( req1Q.first() ) matches
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91 tagged LoadReq .ld : return LoadReq { tag:1, addr:ld.addr };
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92 tagged StoreReq .st : return req1Q.first();
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93 endcase;
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94
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95 // Send out the request
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96 mreqQ.enq(mreq);
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97 nextReq <= REQ0;
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98 req1Q.deq();
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99
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100 endrule
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101
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102 rule returnResp;
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103 traceTiny("mkMemArb", "resp",mrespQ.first());
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104
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105 // Use tag to figure out where to send response
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106 mrespQ.deq();
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107 let tag
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108 = case ( mrespQ.first() ) matches
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109 tagged LoadResp .ld : return ld.tag;
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110 tagged StoreResp .st : return st.tag;
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111 endcase;
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112
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113 if ( tag == 0 )
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114 resp0Q.enq(mrespQ.first());
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115 else
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116 resp1Q.enq(mrespQ.first());
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117
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118 endrule
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119
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120 //-----------------------------------------------------------
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121 // Methods
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122
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123 interface Server cache0_server;
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124 interface Put request = fifofToPut(req0Q);
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125 interface Get response = fifoToGet(resp0Q);
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126 endinterface
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127
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128 interface Server cache1_server;
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129 interface Put request = fifofToPut(req1Q);
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130 interface Get response = fifoToGet(resp1Q);
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131 endinterface
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132
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133 interface Client mmem_client;
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134 interface Get request = fifoToGet(mreqQ);
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135 interface Put response = fifoToPut(mrespQ);
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136 endinterface
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137
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138 endmodule
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139
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140
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