annotate modules/bluespec/Pygar/lab4/ProcTypes.bsv @ 13:6d461680c6d9 pygar svn.14

[svn r14] more stuff
author punk
date Tue, 27 Apr 2010 09:03:28 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1
rlm@8 2 import Trace::*;
rlm@8 3
rlm@8 4 //----------------------------------------------------------------------
rlm@8 5 // Other typedefs
rlm@8 6 //----------------------------------------------------------------------
rlm@8 7
rlm@8 8 typedef Bit#(32) Addr;
rlm@8 9 typedef Int#(18) Stat;
rlm@8 10
rlm@8 11 //----------------------------------------------------------------------
rlm@8 12 // Basic instruction type
rlm@8 13 //----------------------------------------------------------------------
rlm@8 14
rlm@8 15 typedef Bit#(5) Rindx;
rlm@8 16 typedef Bit#(16) Simm;
rlm@8 17 typedef Bit#(16) Zimm;
rlm@8 18 typedef Bit#(8) Epoch;
rlm@8 19 typedef Bit#(5) Shamt;
rlm@8 20 typedef Bit#(26) Target;
rlm@8 21 typedef Bit#(5) CP0indx;
rlm@8 22 typedef Bit#(32) Data;
rlm@8 23
rlm@8 24 typedef enum
rlm@8 25 {
rlm@8 26 Taken,
rlm@8 27 NotTaken
rlm@8 28 }
rlm@8 29 Direction
rlm@8 30 deriving(Bits,Eq);
rlm@8 31
rlm@8 32
rlm@8 33 //----------------------------------------------------------------------
rlm@8 34 // Pipeline typedefs
rlm@8 35 //----------------------------------------------------------------------
rlm@8 36
rlm@8 37 typedef union tagged
rlm@8 38 {
rlm@8 39 Tuple2#(Rindx,Data) ALUWB;
rlm@8 40 Rindx MemWB;
rlm@8 41 Tuple2#(Rindx,Data) CoWB;
rlm@8 42 }
rlm@8 43 WritebackType
rlm@8 44 deriving(Bits,Eq);
rlm@8 45
rlm@8 46 ////////////////////////
rlm@8 47 // I Add Writeback queue type
rlm@8 48 ////////////
rlm@8 49 typedef union tagged
rlm@8 50 {
rlm@8 51 struct {Bit#(32) data; Rindx dest; } WB_ALU;
rlm@8 52 Bit#(32) WB_Host;
rlm@8 53 Rindx WB_Load;
rlm@8 54 void WB_Store;
rlm@8 55 }
rlm@8 56 WBResult deriving(Eq, Bits);
rlm@8 57
rlm@8 58 typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
rlm@8 59 //typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
rlm@8 60
rlm@8 61 typedef union tagged
rlm@8 62 {
rlm@8 63
rlm@8 64 struct { Rindx rbase; Rindx rdst; Simm offset; } LW;
rlm@8 65 struct { Rindx rbase; Rindx rsrc; Simm offset; } SW;
rlm@8 66
rlm@8 67 struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU;
rlm@8 68 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI;
rlm@8 69 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU;
rlm@8 70 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI;
rlm@8 71 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI;
rlm@8 72 struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI;
rlm@8 73 struct { Rindx rdst; Zimm imm; } LUI;
rlm@8 74
rlm@8 75 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL;
rlm@8 76 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL;
rlm@8 77 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA;
rlm@8 78 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV;
rlm@8 79 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV;
rlm@8 80 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV;
rlm@8 81 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU;
rlm@8 82 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU;
rlm@8 83 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND;
rlm@8 84 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR;
rlm@8 85 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR;
rlm@8 86 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR;
rlm@8 87 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT;
rlm@8 88 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU;
rlm@8 89
rlm@8 90 struct { Target target; } J;
rlm@8 91 struct { Target target; } JAL;
rlm@8 92 struct { Rindx rsrc; } JR;
rlm@8 93 struct { Rindx rsrc; Rindx rdst; } JALR;
rlm@8 94 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ;
rlm@8 95 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE;
rlm@8 96 struct { Rindx rsrc; Simm offset; } BLEZ;
rlm@8 97 struct { Rindx rsrc; Simm offset; } BGTZ;
rlm@8 98 struct { Rindx rsrc; Simm offset; } BLTZ;
rlm@8 99 struct { Rindx rsrc; Simm offset; } BGEZ;
rlm@8 100
rlm@8 101 struct { Rindx rdst; CP0indx cop0src; } MFC0;
rlm@8 102 struct { Rindx rsrc; CP0indx cop0dst; } MTC0;
rlm@8 103
rlm@8 104 void ILLEGAL;
rlm@8 105
rlm@8 106 }
rlm@8 107 Instr deriving(Eq);
rlm@8 108
rlm@8 109 //----------------------------------------------------------------------
rlm@8 110 // Pack and Unpack
rlm@8 111 //----------------------------------------------------------------------
rlm@8 112
rlm@8 113 Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000;
rlm@8 114 Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010;
rlm@8 115 Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011;
rlm@8 116 Bit#(6) fcSLLV = 6'b000100;
rlm@8 117 Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110;
rlm@8 118 Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111;
rlm@8 119 Bit#(6) fcADDU = 6'b100001;
rlm@8 120 Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011;
rlm@8 121 Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100;
rlm@8 122 Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101;
rlm@8 123 Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110;
rlm@8 124 Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111;
rlm@8 125 Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010;
rlm@8 126 Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011;
rlm@8 127
rlm@8 128 Bit#(6) opJ = 6'b000010;
rlm@8 129 Bit#(6) opJAL = 6'b000011;
rlm@8 130 Bit#(6) fcJR = 6'b001000;
rlm@8 131 Bit#(6) fcJALR = 6'b001001;
rlm@8 132 Bit#(6) opBEQ = 6'b000100;
rlm@8 133 Bit#(6) opBNE = 6'b000101;
rlm@8 134 Bit#(6) opBLEZ = 6'b000110;
rlm@8 135 Bit#(6) opBGTZ = 6'b000111;
rlm@8 136 Bit#(5) rtBLTZ = 5'b00000;
rlm@8 137 Bit#(5) rtBGEZ = 5'b00001;
rlm@8 138
rlm@8 139 Bit#(5) rsMFC0 = 5'b00000;
rlm@8 140 Bit#(5) rsMTC0 = 5'b00100;
rlm@8 141
rlm@8 142 instance Bits#(Instr,32);
rlm@8 143
rlm@8 144 // Pack Function
rlm@8 145
rlm@8 146 function Bit#(32) pack( Instr instr );
rlm@8 147
rlm@8 148 case ( instr ) matches
rlm@8 149
rlm@8 150 tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset };
rlm@8 151 tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset };
rlm@8 152
rlm@8 153 tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm };
rlm@8 154 tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm };
rlm@8 155 tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm };
rlm@8 156 tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm };
rlm@8 157 tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm };
rlm@8 158 tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm };
rlm@8 159 tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm };
rlm@8 160
rlm@8 161 tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL };
rlm@8 162 tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL };
rlm@8 163 tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA };
rlm@8 164
rlm@8 165 tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV };
rlm@8 166 tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV };
rlm@8 167 tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV };
rlm@8 168
rlm@8 169 tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU };
rlm@8 170 tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU };
rlm@8 171 tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND };
rlm@8 172 tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR };
rlm@8 173 tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR };
rlm@8 174 tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR };
rlm@8 175 tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT };
rlm@8 176 tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU };
rlm@8 177
rlm@8 178 tagged J .it : return { opJ, it.target };
rlm@8 179 tagged JAL .it : return { opJAL, it.target };
rlm@8 180 tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR };
rlm@8 181 tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR };
rlm@8 182 tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset };
rlm@8 183 tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset };
rlm@8 184 tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset };
rlm@8 185 tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset };
rlm@8 186 tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset };
rlm@8 187 tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset };
rlm@8 188
rlm@8 189 tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 };
rlm@8 190 tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 };
rlm@8 191
rlm@8 192 endcase
rlm@8 193
rlm@8 194 endfunction
rlm@8 195
rlm@8 196 // Unpack Function
rlm@8 197
rlm@8 198 function Instr unpack( Bit#(32) instrBits );
rlm@8 199
rlm@8 200 let opcode = instrBits[ 31 : 26 ];
rlm@8 201 let rs = instrBits[ 25 : 21 ];
rlm@8 202 let rt = instrBits[ 20 : 16 ];
rlm@8 203 let rd = instrBits[ 15 : 11 ];
rlm@8 204 let shamt = instrBits[ 10 : 6 ];
rlm@8 205 let funct = instrBits[ 5 : 0 ];
rlm@8 206 let imm = instrBits[ 15 : 0 ];
rlm@8 207 let target = instrBits[ 25 : 0 ];
rlm@8 208
rlm@8 209 case ( opcode )
rlm@8 210
rlm@8 211 opLW : return LW { rbase:rs, rdst:rt, offset:imm };
rlm@8 212 opSW : return SW { rbase:rs, rsrc:rt, offset:imm };
rlm@8 213 opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm };
rlm@8 214 opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm };
rlm@8 215 opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm };
rlm@8 216 opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm };
rlm@8 217 opORI : return ORI { rsrc:rs, rdst:rt, imm:imm };
rlm@8 218 opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm };
rlm@8 219 opLUI : return LUI { rdst:rt, imm:imm };
rlm@8 220 opJ : return J { target:target };
rlm@8 221 opJAL : return JAL { target:target };
rlm@8 222 opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm };
rlm@8 223 opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm };
rlm@8 224 opBLEZ : return BLEZ { rsrc:rs, offset:imm };
rlm@8 225 opBGTZ : return BGTZ { rsrc:rs, offset:imm };
rlm@8 226
rlm@8 227 opFUNC :
rlm@8 228 case ( funct )
rlm@8 229 fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt };
rlm@8 230 fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt };
rlm@8 231 fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt };
rlm@8 232 fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs };
rlm@8 233 fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs };
rlm@8 234 fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs };
rlm@8 235 fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd };
rlm@8 236 fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd };
rlm@8 237 fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd };
rlm@8 238 fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd };
rlm@8 239 fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd };
rlm@8 240 fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd };
rlm@8 241 fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd };
rlm@8 242 fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd };
rlm@8 243 fcJR : return JR { rsrc:rs };
rlm@8 244 fcJALR : return JALR { rsrc:rs, rdst:rd };
rlm@8 245 default : return ILLEGAL;
rlm@8 246 endcase
rlm@8 247
rlm@8 248 opRT :
rlm@8 249 case ( rt )
rlm@8 250 rtBLTZ : return BLTZ { rsrc:rs, offset:imm };
rlm@8 251 rtBGEZ : return BGEZ { rsrc:rs, offset:imm };
rlm@8 252 default : return ILLEGAL;
rlm@8 253 endcase
rlm@8 254
rlm@8 255 opRS :
rlm@8 256 case ( rs )
rlm@8 257 rsMFC0 : return MFC0 { rdst:rt, cop0src:rd };
rlm@8 258 rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd };
rlm@8 259 default : return ILLEGAL;
rlm@8 260 endcase
rlm@8 261
rlm@8 262 default : return ILLEGAL;
rlm@8 263
rlm@8 264 endcase
rlm@8 265
rlm@8 266 endfunction
rlm@8 267
rlm@8 268 endinstance
rlm@8 269
rlm@8 270 //----------------------------------------------------------------------
rlm@8 271 // Trace
rlm@8 272 //----------------------------------------------------------------------
rlm@8 273
rlm@8 274 instance Traceable#(Instr);
rlm@8 275
rlm@8 276 function Action traceTiny( String loc, String ttag, Instr inst );
rlm@8 277 case ( inst ) matches
rlm@8 278
rlm@8 279 tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag );
rlm@8 280 tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag );
rlm@8 281
rlm@8 282 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag );
rlm@8 283 tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag );
rlm@8 284 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag );
rlm@8 285 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag );
rlm@8 286 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag );
rlm@8 287 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag );
rlm@8 288 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag );
rlm@8 289
rlm@8 290 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag );
rlm@8 291 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag );
rlm@8 292 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag );
rlm@8 293 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag );
rlm@8 294 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag );
rlm@8 295 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag );
rlm@8 296
rlm@8 297 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag );
rlm@8 298 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag );
rlm@8 299 tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag );
rlm@8 300 tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag );
rlm@8 301 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag );
rlm@8 302 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag );
rlm@8 303 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag );
rlm@8 304 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag );
rlm@8 305
rlm@8 306 tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag );
rlm@8 307 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag );
rlm@8 308 tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag );
rlm@8 309 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag );
rlm@8 310 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag );
rlm@8 311 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag );
rlm@8 312 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag );
rlm@8 313 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag );
rlm@8 314 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag );
rlm@8 315 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag );
rlm@8 316
rlm@8 317 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag );
rlm@8 318 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag );
rlm@8 319
rlm@8 320 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag );
rlm@8 321
rlm@8 322 endcase
rlm@8 323 endfunction
rlm@8 324
rlm@8 325 function Action traceFull( String loc, String ttag, Instr inst );
rlm@8 326 case ( inst ) matches
rlm@8 327
rlm@8 328 tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase );
rlm@8 329 tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase );
rlm@8 330
rlm@8 331 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
rlm@8 332 tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
rlm@8 333 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
rlm@8 334 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
rlm@8 335 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
rlm@8 336 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
rlm@8 337 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm );
rlm@8 338
rlm@8 339 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
rlm@8 340 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
rlm@8 341 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
rlm@8 342 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
rlm@8 343 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
rlm@8 344 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
rlm@8 345
rlm@8 346 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8 347 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8 348 tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8 349 tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8 350 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8 351 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8 352 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8 353 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8 354
rlm@8 355 tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target );
rlm@8 356 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target );
rlm@8 357 tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc );
rlm@8 358 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc );
rlm@8 359 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
rlm@8 360 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
rlm@8 361 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
rlm@8 362 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
rlm@8 363 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
rlm@8 364 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
rlm@8 365
rlm@8 366 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src );
rlm@8 367 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst );
rlm@8 368
rlm@8 369 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag );
rlm@8 370
rlm@8 371 endcase
rlm@8 372 endfunction
rlm@8 373
rlm@8 374 endinstance
rlm@8 375