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1 // The MIT License
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2
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3 // Copyright (c) 2009 Massachusetts Institute of Technology
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4
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5 // Permission is hereby granted, free of charge, to any person obtaining a copy
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6 // of this software and associated documentation files (the "Software"), to deal
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7 // in the Software without restriction, including without limitation the rights
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8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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9 // copies of the Software, and to permit persons to whom the Software is
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10 // furnished to do so, subject to the following conditions:
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11
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12 // The above copyright notice and this permission notice shall be included in
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13 // all copies or substantial portions of the Software.
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14
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15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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21 // THE SOFTWARE.
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22
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23 import Connectable::*;
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24 import GetPut::*;
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25 import ClientServer::*;
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26 import RegFile::*;
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27 import FIFO::*;
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28 import FIFOF::*;
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29 import RWire::*;
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30
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31 import BFIFO::*;
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32 import MemTypes::*;
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33 import ProcTypes::*;
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34 import Trace::*;
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35
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36 interface ICacheStats;
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37 interface Get#(Stat) num_accesses;
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38 interface Get#(Stat) num_misses;
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39 interface Get#(Stat) num_evictions;
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40 endinterface
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41
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42 interface ICache#( type req_t, type resp_t );
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43
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44 // Interface from processor to cache
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45 interface Server#(req_t,resp_t) proc_server;
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46
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47 // Interface from cache to main memory
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48 interface Client#(MainMemReq,MainMemResp) mmem_client;
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49
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50 // Interface for enabling/disabling statistics
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51 interface Put#(Bool) statsEn_put;
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52
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53 // Interface for collecting statistics
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54 interface ICacheStats stats;
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55
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56 endinterface
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57
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58 //----------------------------------------------------------------------
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59 // Cache Types
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60 //----------------------------------------------------------------------
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61
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62 typedef 10 CacheLineIndexSz;
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63 typedef 20 CacheLineTagSz;
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64 typedef 32 CacheLineSz;
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65
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66 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
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67 typedef Bit#(CacheLineTagSz) CacheLineTag;
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68 typedef Bit#(CacheLineSz) CacheLine;
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69
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70 typedef enum
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71 {
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72 Init,
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73 Access,
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74 Evict,
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75 RefillReq,
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76 RefillResp
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77 }
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78 CacheStage
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79 deriving (Eq,Bits);
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80
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81 //----------------------------------------------------------------------
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82 // Helper functions
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83 //----------------------------------------------------------------------
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84
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85 function Bit#(AddrSz) getAddr( InstReq req );
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86
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87 Bit#(AddrSz) addr = ?;
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88 case ( req ) matches
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89 tagged LoadReq .ld : addr = ld.addr;
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90 tagged StoreReq .st : addr = st.addr;
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91 endcase
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92
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93 return addr;
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94
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95 endfunction
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96
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97 function CacheLineIndex getCacheLineIndex( InstReq req );
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98 Bit#(AddrSz) addr = getAddr(req);
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99 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
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100 return index;
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101 endfunction
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102
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103 function CacheLineTag getCacheLineTag( InstReq req );
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104 Bit#(AddrSz) addr = getAddr(req);
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105 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
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106 return tag;
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107 endfunction
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108
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109 function Bit#(AddrSz) getCacheLineAddr( InstReq req );
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110 Bit#(AddrSz) addr = getAddr(req);
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111 return ((addr >> 2) << 2);
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112 endfunction
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113
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114 //----------------------------------------------------------------------
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115 // Main module
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116 //----------------------------------------------------------------------
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117
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118 (* doc = "synthesis attribute ram_style mkInstCache distributed;" *)
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119 (* synthesize *)
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120 module mkInstCache( ICache#(InstReq,InstResp) );
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121
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122 //-----------------------------------------------------------
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123 // State
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124
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125 Reg#(CacheStage) stage <- mkReg(Init);
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126
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127 RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull();
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128 RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull();
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129
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130 FIFO#(InstReq) reqQ <- mkFIFO();
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131 FIFOF#(InstResp) respQ <- mkBFIFOF1();
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132
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133 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
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134 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
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135
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136 Reg#(CacheLineIndex) initCounter <- mkReg(1);
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137
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138 // Statistics state
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139
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140 Reg#(Bool) statsEn <- mkReg(False);
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141
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142 Reg#(Stat) numAccesses <- mkReg(0);
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143 Reg#(Stat) numMisses <- mkReg(0);
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144 Reg#(Stat) numEvictions <- mkReg(0);
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145
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146 //-----------------------------------------------------------
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147 // Name some wires
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148
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149 let req = reqQ.first();
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150 let reqIndex = getCacheLineIndex(req);
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151 let reqTag = getCacheLineTag(req);
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152 let reqCacheLineAddr = getCacheLineAddr(req);
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153 let refill = mainMemRespQ.first();
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154
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155 //-----------------------------------------------------------
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156 // Initialize
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157
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158 rule init ( stage == Init );
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159 traceTiny("mkInstCacheBlocking", "stage","i");
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160 initCounter <= initCounter + 1;
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161 cacheTagRam.upd(initCounter,Invalid);
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162 if ( initCounter == 0 )
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163 stage <= Access;
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164 endrule
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165
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166 //-----------------------------------------------------------
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167 // Cache access rule
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168
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169 rule access ( (stage == Access) && respQ.notFull() );
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170
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171 // Statistics
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172
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173 if ( statsEn )
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174 numAccesses <= numAccesses + 1;
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175
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176 // Check tag and valid bit to see if this is a hit or a miss
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177
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178 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
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179
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180 // Handle cache hits ...
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181
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182 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
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183 begin
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184 traceTiny("mkInstCacheBlocking", "hitMiss","h");
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185 reqQ.deq();
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186
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187 case ( req ) matches
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188
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189 tagged LoadReq .ld :
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190 respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } );
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191
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192 tagged StoreReq .st :
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193 $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" );
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194
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195 endcase
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196
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197 end
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198
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199 // Handle cache misses - since lines in instruction cache are
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200 // never dirty we can always immediately issue a refill request
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201
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202 else
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203 begin
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204 traceTiny("mkInstCacheBlocking", "hitMiss","m");
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205 if ( statsEn )
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206 numMisses <= numMisses + 1;
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207 if ( statsEn )
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208 if ( isJust(cacheLineTag) )
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209 numEvictions <= numEvictions + 1;
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210
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211 MainMemReq rfReq
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212 = LoadReq { tag : 0,
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213 addr : reqCacheLineAddr };
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214
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215 mainMemReqQ.enq(rfReq);
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216 stage <= RefillResp;
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217 end
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218
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219 endrule
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220
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221 //-----------------------------------------------------------
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222 // Refill response rule
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223
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224 rule refillResp ( stage == RefillResp );
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225 traceTiny("mkInstCacheBlocking", "stage","R");
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226 traceTiny("mkInstCacheBlocking", "refill",refill);
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227
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228 // Write the new data into the cache and update the tag
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229
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230 mainMemRespQ.deq();
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231 case ( mainMemRespQ.first() ) matches
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232
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233 tagged LoadResp .ld :
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234 begin
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235 cacheTagRam.upd(reqIndex,Valid(reqTag));
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236 cacheDataRam.upd(reqIndex,ld.data);
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237 end
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238
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239 tagged StoreResp .st :
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240 noAction;
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241
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242 endcase
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243
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244 stage <= Access;
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245 endrule
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246
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247 //-----------------------------------------------------------
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248 // Methods
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249
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250 interface Client mmem_client;
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251 interface Get request = fifoToGet(mainMemReqQ);
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252 interface Put response = fifoToPut(mainMemRespQ);
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253 endinterface
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254
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255 interface Server proc_server;
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256 interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",toPut(reqQ));
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257 interface Get response = traceGet("mkInstCacheBlocking", "respTiny",toGet(respQ));
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258 endinterface
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259
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260 interface Put statsEn_put = toPut(asReg(statsEn));
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261
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262 interface ICacheStats stats;
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263 interface Get num_accesses = toGet(asReg(numAccesses));
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264 interface Get num_misses = toGet(asReg(numMisses));
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265 interface Get num_evictions = toGet(asReg(numEvictions));
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266 endinterface
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267
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268 endmodule
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269
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