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1 signature SceMiLayer where {
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2 import ¶Assert®¶;
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3
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4 import ¶ConfigReg®¶;
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5
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6 import ¶Counter®¶;
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7
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8 import ¶DReg®¶;
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9
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10 import ¶EdgeDetect®¶;
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11
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12 import ¶FIFOF_®¶;
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13
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14 import ¶FIFOF®¶;
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15
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16 import ¶FIFO®¶;
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17
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18 import ¶HList®¶;
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19
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20 import ¶Inout®¶;
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21
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22 import ¶List®¶;
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23
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24 import BFIFO;
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25
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26 import ¶Clocks®¶;
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27
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28 import ¶DiniPCIE®¶;
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29
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30 import ¶ListN®¶;
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31
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32 import ¶ModuleContextCore®¶;
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33
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34 import ¶ModuleContext®¶;
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35
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36 import ¶Monad®¶;
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37
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38 import ¶PrimArray®¶;
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39
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40 import ¶RWire®¶;
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41
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42 import ¶RegFile®¶;
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43
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44 import ¶Real®¶;
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45
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46 import ¶RevertingVirtualReg®¶;
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47
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48 import ¶Reserved®¶;
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49
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50 import SFIFO;
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51
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52 import ¶Vector®¶;
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53
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54 import ¶BRAMCore®¶;
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55
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56 import ¶BUtils®¶;
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57
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58 import ¶Connectable®¶;
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59
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60 import ¶DefaultValue®¶;
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61
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62 import ¶Gearbox®¶;
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63
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64 import ¶GetPut®¶;
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65
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66 import ¶AlignedFIFOs®¶;
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67
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68 import ¶ClientServer®¶;
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69
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70 import ¶FIFOLevel®¶;
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71
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72 import ¶SceMiDefines®¶;
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73
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74 import ¶SceMiProxies®¶;
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75
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76 import ¶SpecialFIFOs®¶;
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77
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78 import ¶SceMiInternals®¶;
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79
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80 import ¶SceMiAldecMacros®¶;
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81
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82 import ¶SceMiEveMacros®¶;
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83
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84 import ¶SceMiMacros®¶;
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85
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86 import ¶TieOff®¶;
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87
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88 import Trace;
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89
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90 import MemTypes;
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91
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92 import MemArb;
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93
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94 import ProcTypes;
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95
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96 import BRegFile;
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97
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98 import BranchPred;
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99
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100 import DataCacheBlocking;
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101
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102 import InstCacheBlocking;
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103
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104 import Processor;
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105
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106 import Core;
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107
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108 import ¶UnitAppendList®¶;
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109
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110 import ¶XilinxCells®¶;
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111
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112 import ¶SceMiClocks®¶;
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113
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114 import ¶SceMiDiniPCIE®¶;
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115
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116 import ¶SceMiTCP®¶;
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117
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118 import ¶XilinxPCIE®¶;
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119
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120 import ¶SceMiVirtex5PCIE®¶;
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121
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122 import ¶SceMiPCIE®¶;
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123
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124 import ¶SceMiCore®¶;
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125
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126 import ¶SceMiXactors®¶;
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127
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128 import ¶SceMiSerialProbe®¶;
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129
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130 import ¶SceMi®¶;
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131
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132 interface (SceMiLayer.DutWrapper :: *) = {
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133 SceMiLayer.core :: Core.Core;
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134 SceMiLayer.doreset :: ¶GetPut®¶.¶Put®¶ (¶Prelude®¶.¶Bit®¶ 1)
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135 };
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136
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137 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.DutWrapper;
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138
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139 instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.DutWrapper;
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140
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141 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.DutWrapper;
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142
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143 SceMiLayer.mkDutWrapper :: ¶Prelude®¶.¶Module®¶ SceMiLayer.DutWrapper;
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144
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145 SceMiLayer.mkSceMiLayer :: ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶;
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146
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147 SceMiLayer.mkCPUToHostXactor :: Processor.CPUToHost ->
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148 ¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ ->
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149 ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶;
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150
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151 data (SceMiLayer.StatID :: *) =
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152 SceMiLayer.DCACHE_ACCESSES () |
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153 SceMiLayer.DCACHE_MISSES () |
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154 SceMiLayer.DCACHE_WRITEBACKS () |
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155 SceMiLayer.ICACHE_ACCESSES () |
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156 SceMiLayer.ICACHE_MISSES () |
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157 SceMiLayer.ICACHE_EVICTIONS () |
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158 SceMiLayer.PROC_INST () |
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159 SceMiLayer.PROC_CYCLES ();
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160
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161 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.StatID;
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162
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163 instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.StatID;
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164
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165 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.StatID;
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166
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167 instance SceMiLayer ¶Prelude®¶.¶Bits®¶ SceMiLayer.StatID 3;
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168
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169 instance SceMiLayer ¶Prelude®¶.¶Eq®¶ SceMiLayer.StatID;
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170
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171 SceMiLayer.mkCoreStatsXactor :: Core.CoreStats ->
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172 ¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ ->
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173 ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶
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174 }
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