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1 // The MIT License
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2
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3 // Copyright (c) 2009 Massachusetts Institute of Technology
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4
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5 // Permission is hereby granted, free of charge, to any person obtaining a copy
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6 // of this software and associated documentation files (the "Software"), to deal
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7 // in the Software without restriction, including without limitation the rights
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8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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9 // copies of the Software, and to permit persons to whom the Software is
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10 // furnished to do so, subject to the following conditions:
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11
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12 // The above copyright notice and this permission notice shall be included in
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13 // all copies or substantial portions of the Software.
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14
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15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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21 // THE SOFTWARE.
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22
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23 import Connectable::*;
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24 import GetPut::*;
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25 import ClientServer::*;
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26 import RegFile::*;
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27 import FIFO::*;
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28 import FIFOF::*;
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29 import RWire::*;
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30
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31 //AWB includes
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32 `include "asim/provides/low_level_platform_interface.bsh"
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33 `include "asim/provides/soft_connections.bsh"
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34 `include "asim/provides/common_services.bsh"
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35
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36 // Local includes
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37 `include "asim/provides/processor_library.bsh"
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38 `include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh"
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39 `include "asim/provides/common_services.bsh"
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40 `include "asim/dict/STATS_PROCESSOR.bsh"
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41
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42 interface Proc;
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43
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44 // Interface from processor to caches
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45 interface Client#(DataReq,DataResp) dmem_client;
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46 interface Client#(InstReq,InstResp) imem_client;
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47
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48 // Interface for enabling/disabling statistics on the rest of the core
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49 interface Get#(Bool) statsEn_get;
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50
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51 endinterface
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52
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53
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54 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
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55
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56 //-----------------------------------------------------------
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57 // Register file module
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58 //-----------------------------------------------------------
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59
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60 interface RFile;
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61 method Action wr( Rindx rindx, Bit#(32) data );
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62 method Bit#(32) rd1( Rindx rindx );
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63 method Bit#(32) rd2( Rindx rindx );
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64 endinterface
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65
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66 module mkRFile( RFile );
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67
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68 RegFile#(Rindx,Bit#(32)) rfile <- mkRegFileFull();
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69
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70 method Action wr( Rindx rindx, Bit#(32) data );
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71 rfile.upd( rindx, data );
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72 endmethod
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73
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74 method Bit#(32) rd1( Rindx rindx );
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75 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
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76 endmethod
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77
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78 method Bit#(32) rd2( Rindx rindx );
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79 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
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80 endmethod
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81
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82 endmodule
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83
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84 //-----------------------------------------------------------
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85 // Helper functions
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86 //-----------------------------------------------------------
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87
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88 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
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89 return zeroExtend( pack( signedLT(val1,val2) ) );
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90 endfunction
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91
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92 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
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93 return zeroExtend( pack( val1 < val2 ) );
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94 endfunction
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95
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96 function Bit#(32) rshft( Bit#(32) val );
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97 return zeroExtend(val[4:0]);
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98 endfunction
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99
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100 //-----------------------------------------------------------
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101 // Reference processor
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102 //-----------------------------------------------------------
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103
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104
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105 module [CONNECTED_MODULE] mkProc( Proc );
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106
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107 //-----------------------------------------------------------
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108 // Debug port
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109
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110 ServerStub_PROCESSORSYSTEMRRR server_stub <- mkServerStub_PROCESSORSYSTEMRRR();
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111
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112 //-----------------------------------------------------------
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113 // State
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114
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115 // Standard processor state
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116
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117 Reg#(Addr) pc <- mkReg(32'h00001000);
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118 Reg#(Stage) stage <- mkReg(PCgen);
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119 RFile rf <- mkRFile;
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120
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121 // Coprocessor state - connected by way of RRR
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122
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123 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
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124
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125 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
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126
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127 Reg#(Bool) cp0_statsEn <- mkReg(False);
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128
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129 // Memory request/response state
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130
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131 FIFO#(InstReq) instReqQ <- mkBFIFO1();
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132 FIFO#(InstResp) instRespQ <- mkFIFO();
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133
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134 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
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135 FIFO#(DataResp) dataRespQ <- mkFIFO();
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136
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137 // Statistics state
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138 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
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139 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
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140
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141 //-----------------------------------------------------------
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142 // Rules
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143
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144 let pc_plus4 = pc + 4;
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145
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146 rule pcgen ( stage == PCgen );
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147 traceTiny("mkProc", "pc",pc);
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148 traceTiny("mkProc", "pcgen","P");
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149 instReqQ.enq( LoadReq{ addr:pc, tag:0 } );
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150 stage <= Exec;
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151 endrule
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152
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153 rule exec ( stage == Exec );
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154
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155 // Some abbreviations
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156 let sext = signExtend;
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157 let zext = zeroExtend;
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158 let sra = signedShiftRight;
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159
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160 // Get the instruction
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161
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162 instRespQ.deq();
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163 Instr inst
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164 = case ( instRespQ.first() ) matches
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165 tagged LoadResp .ld : return unpack(ld.data);
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166 tagged StoreResp .st : return ?;
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167 endcase;
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168
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169 // Some default variables
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170 Stage next_stage = PCgen;
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171 Addr next_pc = pc_plus4;
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172
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173 // Tracing
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174 traceTiny("mkProc", "exec","X");
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175 traceTiny("mkProc", "exInstTiny",inst);
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176 traceFull("mkProc", "exInstFull",inst);
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177
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178 case ( inst ) matches
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179
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180 // -- Memory Ops ------------------------------------------------
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181
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182 tagged LW .it :
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183 begin
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184 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
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185 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
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186 next_stage = Writeback;
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187 end
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188
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189 tagged SW .it :
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190 begin
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191 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
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192 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd1(it.rsrc) } );
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193 next_stage = Writeback;
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194 end
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195
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196 // -- Simple Ops ------------------------------------------------
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197
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198 tagged ADDIU .it : rf.wr( it.rdst, rf.rd1(it.rsrc) + sext(it.imm) );
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199 tagged SLTI .it : rf.wr( it.rdst, slt( rf.rd1(it.rsrc), sext(it.imm) ) );
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200 tagged SLTIU .it : rf.wr( it.rdst, sltu( rf.rd1(it.rsrc), sext(it.imm) ) );
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201 tagged ANDI .it :
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202 begin
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203 Bit#(32) zext_it_imm = zext(it.imm);
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204 rf.wr( it.rdst, rf.rd1(it.rsrc) & zext_it_imm );
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205 end
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206 tagged ORI .it :
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207 begin
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208 Bit#(32) zext_it_imm = zext(it.imm);
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209 rf.wr( it.rdst, rf.rd1(it.rsrc) | zext_it_imm );
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210 end
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211 tagged XORI .it :
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212 begin
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213 Bit#(32) zext_it_imm = zext(it.imm);
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214 rf.wr( it.rdst, rf.rd1(it.rsrc) ^ zext_it_imm );
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215 end
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216 tagged LUI .it :
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217 begin
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218 Bit#(32) zext_it_imm = zext(it.imm);
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219 rf.wr( it.rdst, (zext_it_imm << 32'd16) );
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220 end
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221
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222 tagged SLL .it :
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223 begin
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224 Bit#(32) zext_it_shamt = zext(it.shamt);
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225 rf.wr( it.rdst, rf.rd1(it.rsrc) << zext_it_shamt );
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226 end
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227 tagged SRL .it :
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228 begin
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229 Bit#(32) zext_it_shamt = zext(it.shamt);
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230 rf.wr( it.rdst, rf.rd1(it.rsrc) >> zext_it_shamt );
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231 end
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232 tagged SRA .it :
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233 begin
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234 Bit#(32) zext_it_shamt = zext(it.shamt);
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235 rf.wr( it.rdst, sra( rf.rd1(it.rsrc), zext_it_shamt ));
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236 end
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237 tagged SLLV .it : rf.wr( it.rdst, rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) );
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238 tagged SRLV .it : rf.wr( it.rdst, rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) );
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239 tagged SRAV .it : rf.wr( it.rdst, sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) );
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240 tagged ADDU .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) );
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241 tagged SUBU .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) );
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242 tagged AND .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) );
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243 tagged OR .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) );
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244 tagged XOR .it : rf.wr( it.rdst, rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) );
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245 tagged NOR .it : rf.wr( it.rdst, ~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) );
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246 tagged SLT .it : rf.wr( it.rdst, slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) );
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247 tagged SLTU .it : rf.wr( it.rdst, sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) );
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248
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249 // -- Branches --------------------------------------------------
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250
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251 tagged BLEZ .it :
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252 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
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253 next_pc = pc_plus4 + (sext(it.offset) << 2);
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254
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255 tagged BGTZ .it :
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256 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
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257 next_pc = pc_plus4 + (sext(it.offset) << 2);
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258
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259 tagged BLTZ .it :
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260 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
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261 next_pc = pc_plus4 + (sext(it.offset) << 2);
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262
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263 tagged BGEZ .it :
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264 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
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265 next_pc = pc_plus4 + (sext(it.offset) << 2);
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266
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267 tagged BEQ .it :
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268 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
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269 next_pc = pc_plus4 + (sext(it.offset) << 2);
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270
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271 tagged BNE .it :
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272 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
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273 next_pc = pc_plus4 + (sext(it.offset) << 2);
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274
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275 // -- Jumps -----------------------------------------------------
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276
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277 tagged J .it :
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278 next_pc = { pc_plus4[31:28], it.target, 2'b0 };
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279
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280 tagged JR .it :
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281 next_pc = rf.rd1(it.rsrc);
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282
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283 tagged JAL .it :
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284 begin
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285 rf.wr( 31, pc_plus4 );
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286 next_pc = { pc_plus4[31:28], it.target, 2'b0 };
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287 end
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288
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289 tagged JALR .it :
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290 begin
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291 rf.wr( it.rdst, pc_plus4 );
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292 next_pc = rf.rd1(it.rsrc);
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293 end
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rlm@8
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294
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rlm@8
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295 // -- Cop0 ------------------------------------------------------
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rlm@8
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296
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rlm@8
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297 tagged MTC0 .it :
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rlm@8
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298 case ( it.cop0dst )
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rlm@8
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299 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
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rlm@8
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300 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
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rlm@8
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301 default :
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rlm@8
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302 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
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rlm@8
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303 endcase
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rlm@8
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304
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rlm@8
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305 tagged MFC0 .it :
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rlm@8
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306 case ( it.cop0src )
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rlm@8
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307 5'd10 : rf.wr( it.rdst, zext(pack(cp0_statsEn)) );
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rlm@8
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308 5'd20 : rf.wr( it.rdst, cp0_fromhost );
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rlm@8
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309 5'd21 : rf.wr( it.rdst, cp0_tohost );
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rlm@8
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310 default :
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rlm@8
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311 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
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rlm@8
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312 endcase
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rlm@8
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313
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rlm@8
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314 // -- Illegal ---------------------------------------------------
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rlm@8
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315
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rlm@8
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316 default :
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rlm@8
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317 $display( " RTL-ERROR : %m : Illegal instruction !" );
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rlm@8
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318
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rlm@8
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319 endcase
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rlm@8
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320
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rlm@8
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321 stage <= next_stage;
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rlm@8
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322 pc <= next_pc;
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rlm@8
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323
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rlm@8
|
324 if ( cp0_statsEn )
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rlm@8
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325 num_inst.incr();
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rlm@8
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326
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|
rlm@8
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327 endrule
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rlm@8
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328
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|
rlm@8
|
329 rule writeback ( stage == Writeback );
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rlm@8
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330 traceTiny("mkProc", "writeback","W");
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rlm@8
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331
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rlm@8
|
332 dataRespQ.deq();
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rlm@8
|
333 case ( dataRespQ.first() ) matches
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|
rlm@8
|
334 tagged LoadResp .ld : rf.wr( truncate(ld.tag), ld.data );
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|
rlm@8
|
335 tagged StoreResp .st : noAction;
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|
rlm@8
|
336 endcase
|
|
rlm@8
|
337
|
|
rlm@8
|
338 stage <= PCgen;
|
|
rlm@8
|
339 endrule
|
|
rlm@8
|
340
|
|
rlm@8
|
341 rule inc_num_cycles;
|
|
rlm@8
|
342 if ( cp0_statsEn )
|
|
rlm@8
|
343 num_cycles.incr();
|
|
rlm@8
|
344 endrule
|
|
rlm@8
|
345
|
|
rlm@8
|
346 rule handleCPUToHost;
|
|
rlm@8
|
347 let req <- server_stub.acceptRequest_ReadCPUToHost();
|
|
rlm@8
|
348 case (req)
|
|
rlm@8
|
349 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
|
|
rlm@8
|
350 1: server_stub.sendResponse_ReadCPUToHost(pc);
|
|
rlm@8
|
351 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
|
|
rlm@8
|
352 endcase
|
|
rlm@8
|
353 endrule
|
|
rlm@8
|
354
|
|
rlm@8
|
355
|
|
rlm@8
|
356
|
|
rlm@8
|
357 //-----------------------------------------------------------
|
|
rlm@8
|
358 // Methods
|
|
rlm@8
|
359
|
|
rlm@8
|
360 interface Client imem_client;
|
|
rlm@8
|
361 interface Get request = fifoToGet(instReqQ);
|
|
rlm@8
|
362 interface Put response = fifoToPut(instRespQ);
|
|
rlm@8
|
363 endinterface
|
|
rlm@8
|
364
|
|
rlm@8
|
365 interface Client dmem_client;
|
|
rlm@8
|
366 interface Get request = fifoToGet(dataReqQ);
|
|
rlm@8
|
367 interface Put response = fifoToPut(dataRespQ);
|
|
rlm@8
|
368 endinterface
|
|
rlm@8
|
369
|
|
rlm@8
|
370 interface Get statsEn_get = regToGet(cp0_statsEn);
|
|
rlm@8
|
371
|
|
rlm@8
|
372 endmodule
|
|
rlm@8
|
373
|
