pygar: modules/bluespec/Pygar/core/Processor.bsv annotate

annotate modules/bluespec/Pygar/core/Processor.bsv @ 11:50af57801d6e pygar svn.12

[svn r12] working on getting audio pipe processor working

author	punk
date	Sun, 25 Apr 2010 08:31:47 -0400
parents	74716e9a81cc
children	394aa40fd812

rev	line source
rlm@8	1 /// The MIT License
rlm@8	2
rlm@8	3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8	4
rlm@8	5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8	6 // of this software and associated documentation files (the "Software"), to deal
rlm@8	7 // in the Software without restriction, including without limitation the rights
rlm@8	8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8	9 // copies of the Software, and to permit persons to whom the Software is
rlm@8	10 // furnished to do so, subject to the following conditions:
rlm@8	11
rlm@8	12 // The above copyright notice and this permission notice shall be included in
rlm@8	13 // all copies or substantial portions of the Software.
rlm@8	14
rlm@8	15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8	16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8	17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8	18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8	19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8	20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8	21 // THE SOFTWARE.
rlm@8	22
rlm@8	23 import Connectable::*;
rlm@8	24 import GetPut::*;
rlm@8	25 import ClientServer::*;
rlm@8	26 import RegFile::*;
rlm@8	27
rlm@8	28 import FIFO::*;
rlm@8	29 import FIFOF::*;
rlm@8	30 import SFIFO::*;
rlm@8	31 import RWire::*;
rlm@8	32
punk@11	33 import Trace::*;
rlm@8	34 import BFIFO::*;
rlm@8	35 import MemTypes::*;
rlm@8	36 import ProcTypes::*;
rlm@8	37 import BRegFile::*;
rlm@8	38 import BranchPred::*;
rlm@8	39 //import PathTypes::*; This is only there to force the debugging
rlm@8	40
rlm@8	41 //AWB includes
rlm@8	42 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8	43 `include "asim/provides/soft_connections.bsh"
rlm@8	44 `include "asim/provides/common_services.bsh"
rlm@8	45
rlm@8	46 // Local includes
punk@11	47 //`include "asim/provides/processor_library.bsh" (included above directly)
rlm@8	48 `include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh"
rlm@8	49 `include "asim/provides/common_services.bsh"
rlm@8	50 `include "asim/dict/STATS_PROCESSOR.bsh"
rlm@8	51
punk@11	52 // Local includes. Look for the correspondingly named .awb files
punk@11	53 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@11	54 // to find the actual Bluespec files which are used to generate
punk@11	55 // these includes. These files are specific to this audio processing
punk@11	56 // pipeline
punk@11	57
punk@11	58 `include "asim/provides/audio_processor_types.bsh"
rlm@8	59
rlm@8	60 interface CPUToHost;
rlm@8	61 method Bit#(32) cpuToHost(int req);
rlm@8	62 endinterface
rlm@8	63
rlm@8	64 interface Proc;
rlm@8	65
rlm@8	66 // Interface from processor to caches
rlm@8	67 interface Client#(DataReq,DataResp) dmem_client;
rlm@8	68 interface Client#(InstReq,InstResp) imem_client;
rlm@8	69
rlm@8	70 // Interface for enabling/disabling statistics on the rest of the core
rlm@8	71 interface Get#(Bool) statsEn_get;
rlm@8	72
rlm@8	73 // Interface to host
rlm@8	74 interface CPUToHost tohost;
rlm@8	75
punk@11	76 // Interface to Audio Pipeline
punk@11	77 interface Audio audio;
punk@11	78
rlm@8	79 endinterface
rlm@8	80
punk@11	81 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
punk@11	82 interface Audio;
punk@11	83 interface Put#(AudioProcessorUnit) audioSampleInput;
punk@11	84 interface Get#(AudioProcessorUnit) audioSampleOutput;
punk@11	85 endinterface
rlm@8	86
rlm@8	87 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
rlm@8	88
rlm@8	89 //-----------------------------------------------------------
rlm@8	90 // Register file module
rlm@8	91 //-----------------------------------------------------------
rlm@8	92
rlm@8	93 interface BRFile;
rlm@8	94 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	95 method Bit#(32) rd1( Rindx rindx );
rlm@8	96 method Bit#(32) rd2( Rindx rindx );
rlm@8	97 endinterface
rlm@8	98
rlm@8	99 module mkBRFile( BRFile );
rlm@8	100
rlm@8	101 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
rlm@8	102
rlm@8	103 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	104 rfile.upd( rindx, data );
rlm@8	105 endmethod
rlm@8	106
rlm@8	107 method Bit#(32) rd1( Rindx rindx );
rlm@8	108 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	109 endmethod
rlm@8	110
rlm@8	111 method Bit#(32) rd2( Rindx rindx );
rlm@8	112 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	113 endmethod
rlm@8	114
rlm@8	115 endmodule
rlm@8	116
rlm@8	117 //-----------------------------------------------------------
rlm@8	118 // Helper functions
rlm@8	119 //-----------------------------------------------------------
rlm@8	120
rlm@8	121 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
rlm@8	122 return zeroExtend( pack( signedLT(val1,val2) ) );
rlm@8	123 endfunction
rlm@8	124
rlm@8	125 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
rlm@8	126 return zeroExtend( pack( val1 < val2 ) );
rlm@8	127 endfunction
rlm@8	128
rlm@8	129 function Bit#(32) rshft( Bit#(32) val );
rlm@8	130 return zeroExtend(val[4:0]);
rlm@8	131 endfunction
rlm@8	132
rlm@8	133
rlm@8	134 //-----------------------------------------------------------
rlm@8	135 // Find funct for wbQ
rlm@8	136 //-----------------------------------------------------------
rlm@8	137 function Bool findwbf(Rindx fVal, WBResult cmpVal);
rlm@8	138 case (cmpVal) matches
rlm@8	139 tagged WB_ALU {data:.res, dest:.rd} :
rlm@8	140 return (fVal == rd);
rlm@8	141 tagged WB_Load .rd :
rlm@8	142 return (fVal == rd);
rlm@8	143 tagged WB_Store .st :
rlm@8	144 return False;
rlm@8	145 tagged WB_Host .x :
rlm@8	146 return False;
rlm@8	147 endcase
rlm@8	148 endfunction
rlm@8	149
rlm@8	150
rlm@8	151 //-----------------------------------------------------------
rlm@8	152 // Stall funct for wbQ
rlm@8	153 //-----------------------------------------------------------
rlm@8	154 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
rlm@8	155 case (inst) matches
rlm@8	156 // -- Memory Ops ------------------------------------------------
rlm@8	157 tagged LW .it :
rlm@8	158 return f.find(it.rbase);
rlm@8	159 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
rlm@8	160 return (f.find(addr) \|\| f.find2(dreg));
rlm@8	161
rlm@8	162 // -- Simple Ops ------------------------------------------------
rlm@8	163 tagged ADDIU .it : return f.find(it.rsrc);
rlm@8	164 tagged SLTI .it : return f.find(it.rsrc);
rlm@8	165 tagged SLTIU .it : return f.find(it.rsrc);
rlm@8	166 tagged ANDI .it : return f.find(it.rsrc);
rlm@8	167 tagged ORI .it : return f.find(it.rsrc);
rlm@8	168 tagged XORI .it : return f.find(it.rsrc);
rlm@8	169
rlm@8	170 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
rlm@8	171 tagged SLL .it : return f.find(it.rsrc);
rlm@8	172 tagged SRL .it : return f.find(it.rsrc);
rlm@8	173 tagged SRA .it : return f.find(it.rsrc);
rlm@8	174 tagged SLLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	175 tagged SRLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	176 tagged SRAV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	177 tagged ADDU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	178 tagged SUBU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	179 tagged AND .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	180 tagged OR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	181 tagged XOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	182 tagged NOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	183 tagged SLT .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	184 tagged SLTU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	185
rlm@8	186
rlm@8	187 // -- Branches --------------------------------------------------
rlm@8	188
rlm@8	189 tagged BLEZ .it : return (f.find(it.rsrc));
rlm@8	190 tagged BGTZ .it : return (f.find(it.rsrc));
rlm@8	191 tagged BLTZ .it : return (f.find(it.rsrc));
rlm@8	192 tagged BGEZ .it : return (f.find(it.rsrc));
rlm@8	193 tagged BEQ .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	194 tagged BNE .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	195
rlm@8	196 // -- Jumps -----------------------------------------------------
rlm@8	197
rlm@8	198 tagged J .it : return False;
rlm@8	199 tagged JR .it : return f.find(it.rsrc);
rlm@8	200 tagged JALR .it : return f.find(it.rsrc);
rlm@8	201 tagged JAL .it : return False;
rlm@8	202
rlm@8	203 // -- Cop0 ------------------------------------------------------
rlm@8	204
rlm@8	205 tagged MTC0 .it : return f.find(it.rsrc);
rlm@8	206 tagged MFC0 .it : return False;
rlm@8	207
rlm@8	208 // -- Illegal ---------------------------------------------------
rlm@8	209
rlm@8	210 default : return False;
rlm@8	211
rlm@8	212 endcase
rlm@8	213 endfunction
rlm@8	214 //-----------------------------------------------------------
rlm@8	215 // Reference processor
rlm@8	216 //-----------------------------------------------------------
rlm@8	217
rlm@8	218
rlm@8	219 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
rlm@8	220 //(* synthesize *)
rlm@8	221
rlm@8	222 module [CONNECTED_MODULE] mkProc( Proc );
rlm@8	223
rlm@8	224 //-----------------------------------------------------------
rlm@8	225 // Debug port
rlm@8	226
rlm@8	227 ServerStub_PROCESSORSYSTEMRRR server_stub <- mkServerStub_PROCESSORSYSTEMRRR();
rlm@8	228
rlm@8	229
rlm@8	230 //-----------------------------------------------------------
rlm@8	231 // State
rlm@8	232
rlm@8	233 // Standard processor state
rlm@8	234
rlm@8	235 Reg#(Addr) pc <- mkReg(32'h00001000);
rlm@8	236 Reg#(Epoch) epoch <- mkReg(0);
rlm@8	237 Reg#(Stage) stage <- mkReg(PCgen);
rlm@8	238 BRFile rf <- mkBRFile;
rlm@8	239
rlm@8	240 // Branch Prediction
rlm@8	241 BranchPred bp <- mkBranchPred();
rlm@8	242 FIFO#(PCStat) execpc <- mkLFIFO();
rlm@8	243
rlm@8	244 // Pipelines
rlm@8	245 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
rlm@8	246 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
rlm@8	247
rlm@8	248 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
rlm@8	249 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
rlm@8	250 Reg#(Bool) cp0_statsEn <- mkReg(False);
rlm@8	251
rlm@8	252 // Memory request/response state
rlm@8	253
rlm@8	254 FIFO#(InstReq) instReqQ <- mkBFIFO1();
rlm@8	255 FIFO#(InstResp) instRespQ <- mkFIFO();
rlm@8	256
rlm@8	257 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
rlm@8	258 FIFO#(DataResp) dataRespQ <- mkFIFO();
rlm@8	259
punk@11	260 // Audio I/O
punk@11	261 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
punk@11	262 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
punk@11	263
punk@11	264
punk@11	265 // Statistics state (2010)
punk@11	266 // Reg#(Stat) num_cycles <- mkReg(0);
punk@11	267 // Reg#(Stat) num_inst <- mkReg(0);
rlm@8	268
rlm@8	269 //Or:
punk@11	270 // Statistics state
punk@11	271 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
punk@11	272 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
rlm@8	273
rlm@8	274 //-----------------------------------------------------------
rlm@8	275 // Rules
rlm@8	276
rlm@8	277 (* descending_urgency = "exec, pcgen" *)
rlm@8	278 rule pcgen; //( stage == PCgen );
rlm@8	279 let pc_plus4 = pc + 4;
rlm@8	280
rlm@8	281 traceTiny("mkProc", "pc",pc);
rlm@8	282 traceTiny("mkProc", "pcgen","P");
rlm@8	283 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
rlm@8	284
rlm@8	285 let next_pc = bp.get(pc);
rlm@8	286 if (next_pc matches tagged Valid .npc)
rlm@8	287 begin
rlm@8	288 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
rlm@8	289 pc <= npc;
rlm@8	290 end
rlm@8	291 else
rlm@8	292 begin
rlm@8	293 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
rlm@8	294 pc <= pc_plus4;
rlm@8	295 end
rlm@8	296
rlm@8	297 endrule
rlm@8	298
rlm@8	299 rule discard (instRespQ.first() matches tagged LoadResp .ld
rlm@8	300 &&& ld.tag != epoch);
rlm@8	301 traceTiny("mkProc", "stage", "D");
rlm@8	302 instRespQ.deq();
rlm@8	303 endrule
rlm@8	304
rlm@8	305 (* conflict_free = "exec, writeback" *)
rlm@8	306 rule exec (instRespQ.first() matches tagged LoadResp.ld
rlm@8	307 &&& (ld.tag == epoch)
rlm@8	308 &&& unpack(ld.data) matches .inst
rlm@8	309 &&& !stall(inst, wbQ));
rlm@8	310
rlm@8	311 // Some abbreviations
rlm@8	312 let sext = signExtend;
rlm@8	313 let zext = zeroExtend;
rlm@8	314 let sra = signedShiftRight;
rlm@8	315
rlm@8	316 // Get the instruction
rlm@8	317
rlm@8	318 instRespQ.deq();
rlm@8	319 Instr inst
rlm@8	320 = case ( instRespQ.first() ) matches
rlm@8	321 tagged LoadResp .ld : return unpack(ld.data);
rlm@8	322 tagged StoreResp .st : return ?;
rlm@8	323 endcase;
rlm@8	324
rlm@8	325 // Get the PC info
rlm@8	326 let instrpc = pcQ.first().qpc;
rlm@8	327 let pc_plus4 = instrpc + 4;
rlm@8	328
rlm@8	329 Bool branchTaken = False;
rlm@8	330 Addr newPC = pc_plus4;
rlm@8	331
rlm@8	332 // Tracing
rlm@8	333 traceTiny("mkProc", "exec","X");
rlm@8	334 traceTiny("mkProc", "exInstTiny",inst);
rlm@8	335 traceFull("mkProc", "exInstFull",inst);
rlm@8	336
rlm@8	337 case ( inst ) matches
rlm@8	338
rlm@8	339 // -- Memory Ops ------------------------------------------------
rlm@8	340
rlm@8	341 tagged LW .it :
rlm@8	342 begin
rlm@8	343 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	344 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
rlm@8	345 wbQ.enq(tagged WB_Load it.rdst);
rlm@8	346 end
rlm@8	347
rlm@8	348 tagged SW .it :
rlm@8	349 begin
rlm@8	350 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	351 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
rlm@8	352 wbQ.enq(tagged WB_Store);
rlm@8	353 end
rlm@8	354
rlm@8	355 // -- Simple Ops ------------------------------------------------
rlm@8	356
rlm@8	357 tagged ADDIU .it :
rlm@8	358 begin
rlm@8	359 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
rlm@8	360 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
rlm@8	361 end
rlm@8	362 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
rlm@8	363 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
rlm@8	364 tagged ANDI .it :
rlm@8	365 begin
rlm@8	366 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	367 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
rlm@8	368 end
rlm@8	369 tagged ORI .it :
rlm@8	370 begin
rlm@8	371 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	372 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) \| zext_it_imm)} );
rlm@8	373 end
rlm@8	374 tagged XORI .it :
rlm@8	375 begin
rlm@8	376 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	377 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
rlm@8	378 end
rlm@8	379 tagged LUI .it :
rlm@8	380 begin
rlm@8	381 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	382 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
rlm@8	383 end
rlm@8	384
rlm@8	385 tagged SLL .it :
rlm@8	386 begin
rlm@8	387 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	388 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
rlm@8	389 end
rlm@8	390 tagged SRL .it :
rlm@8	391 begin
rlm@8	392 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	393 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
rlm@8	394 end
rlm@8	395 tagged SRA .it :
rlm@8	396 begin
rlm@8	397 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	398 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
rlm@8	399 end
rlm@8	400 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
rlm@8	401 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
rlm@8	402 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
rlm@8	403 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
rlm@8	404 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
rlm@8	405 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
rlm@8	406 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2) )} );
rlm@8	407 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
rlm@8	408 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2)) )} );
rlm@8	409 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	410 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	411
rlm@8	412 // -- Branches --------------------------------------------------
rlm@8	413
rlm@8	414 tagged BLEZ .it :
rlm@8	415 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
rlm@8	416 begin
rlm@8	417 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	418 branchTaken = True;
rlm@8	419 end
rlm@8	420
rlm@8	421 tagged BGTZ .it :
rlm@8	422 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
rlm@8	423 begin
rlm@8	424 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	425 branchTaken = True;
rlm@8	426 end
rlm@8	427
rlm@8	428 tagged BLTZ .it :
rlm@8	429 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
rlm@8	430 begin
rlm@8	431 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	432 branchTaken = True;
rlm@8	433 end
rlm@8	434
rlm@8	435 tagged BGEZ .it :
rlm@8	436 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
rlm@8	437 begin
rlm@8	438 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	439 branchTaken = True;
rlm@8	440 end
rlm@8	441
rlm@8	442 tagged BEQ .it :
rlm@8	443 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
rlm@8	444 begin
rlm@8	445 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	446 branchTaken = True;
rlm@8	447 end
rlm@8	448
rlm@8	449 tagged BNE .it :
rlm@8	450 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
rlm@8	451 begin
rlm@8	452 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	453 branchTaken = True;
rlm@8	454 end
rlm@8	455
rlm@8	456 // -- Jumps -----------------------------------------------------
rlm@8	457
rlm@8	458 tagged J .it :
rlm@8	459 begin
rlm@8	460 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	461 branchTaken = True;
rlm@8	462 end
rlm@8	463
rlm@8	464 tagged JR .it :
rlm@8	465 begin
rlm@8	466 newPC = rf.rd1(it.rsrc);
rlm@8	467 branchTaken = True;
rlm@8	468 end
rlm@8	469
rlm@8	470 tagged JAL .it :
rlm@8	471 begin
rlm@8	472 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
rlm@8	473 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	474 branchTaken = True;
rlm@8	475 end
rlm@8	476
rlm@8	477 tagged JALR .it :
rlm@8	478 begin
rlm@8	479 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
rlm@8	480 newPC = rf.rd1(it.rsrc);
rlm@8	481 branchTaken = True;
rlm@8	482 end
rlm@8	483
rlm@8	484 // -- Cop0 ------------------------------------------------------
rlm@8	485
rlm@8	486 tagged MTC0 .it :
rlm@8	487 begin
rlm@8	488 case ( it.cop0dst )
rlm@8	489 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
rlm@8	490 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
rlm@8	491 default :
rlm@8	492 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
rlm@8	493 endcase
rlm@8	494 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
rlm@8	495 end
rlm@8	496
rlm@8	497 //this is host stuff?
rlm@8	498 tagged MFC0 .it :
rlm@8	499 begin
rlm@8	500 case ( it.cop0src )
rlm@8	501 // not actually an ALU instruction but don't have the format otherwise
rlm@8	502 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
rlm@8	503 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
rlm@8	504 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
rlm@8	505 default :
rlm@8	506 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
rlm@8	507 endcase
rlm@8	508 end
rlm@8	509
rlm@8	510 // -- Illegal ---------------------------------------------------
rlm@8	511
rlm@8	512 default :
rlm@8	513 $display( " RTL-ERROR : %m : Illegal instruction !" );
rlm@8	514
rlm@8	515 endcase
rlm@8	516
rlm@8	517 //evaluate branch prediction
rlm@8	518 Addr ppc = pcQ.first().qnxtpc; //predicted branch
rlm@8	519 if (ppc != newPC) //prediction wrong
rlm@8	520 begin
rlm@8	521 epoch <= pcQ.first().qepoch + 1;
rlm@8	522 bp.upd(instrpc, newPC); //update branch predictor
rlm@8	523 pcQ.clear();
rlm@8	524 pc <= newPC;
rlm@8	525 end
rlm@8	526 else
rlm@8	527 pcQ.deq();
rlm@8	528
rlm@8	529 if ( cp0_statsEn )
punk@11	530 num_inst.incr();
rlm@8	531
rlm@8	532 endrule
rlm@8	533
rlm@8	534 rule writeback; // ( stage == Writeback );
rlm@8	535 traceTiny("mkProc", "writeback","W");
rlm@8	536
rlm@8	537
rlm@8	538 // get what to do off the writeback queue
rlm@8	539 wbQ.deq();
rlm@8	540 case (wbQ.first()) matches
rlm@8	541 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
rlm@8	542 tagged WB_Load .regWr :
rlm@8	543 begin
rlm@8	544 dataRespQ.deq();
rlm@8	545 if (dataRespQ.first() matches tagged LoadResp .ld)
rlm@8	546 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
rlm@8	547 end
rlm@8	548 tagged WB_Store : dataRespQ.deq();
rlm@8	549 tagged WB_Host .dat : noAction;
rlm@8	550 endcase
rlm@8	551
rlm@8	552 endrule
rlm@8	553
rlm@8	554 rule inc_num_cycles;
rlm@8	555 if ( cp0_statsEn )
punk@11	556 num_cycles.incr();
rlm@8	557 endrule
punk@11	558
punk@11	559 (* conservative_implicit_conditions *)
punk@11	560 rule handleCPUToHost;
punk@11	561 let req <- server_stub.acceptRequest_ReadCPUToHost();
punk@11	562 case (req)
punk@11	563 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
punk@11	564 1: server_stub.sendResponse_ReadCPUToHost(pc);
punk@11	565 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
punk@11	566 endcase
punk@11	567 endrule
punk@11	568
punk@11	569 // for now, we don't do anything.
punk@11	570 rule connectAudioReqResp;
punk@11	571 $display("FIR copies a data");
punk@11	572 outAudioFifo.enq(inAudioFifo.first);
punk@11	573 outAudioFifo.deq;
punk@11	574 endrule
rlm@8	575
rlm@8	576 //-----------------------------------------------------------
rlm@8	577 // Methods
rlm@8	578
rlm@8	579 interface Client imem_client;
rlm@8	580 interface Get request = toGet(instReqQ);
rlm@8	581 interface Put response = toPut(instRespQ);
rlm@8	582 endinterface
rlm@8	583
rlm@8	584 interface Client dmem_client;
rlm@8	585 interface Get request = toGet(dataReqQ);
rlm@8	586 interface Put response = toPut(dataRespQ);
rlm@8	587 endinterface
rlm@8	588
rlm@8	589 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
rlm@8	590
rlm@8	591 interface CPUToHost tohost;
rlm@8	592 method Bit#(32) cpuToHost(int req);
rlm@8	593 return (case (req)
rlm@8	594 0: cp0_tohost;
rlm@8	595 1: pc;
rlm@8	596 2: zeroExtend(pack(stage));
rlm@8	597 endcase);
rlm@8	598 endmethod
rlm@8	599 endinterface
rlm@8	600
punk@11	601 interface Audio audio;
punk@11	602 interface audioSampleInput = fifoToPut(inAudioFifo);
punk@11	603 interface audioSampleOutput = fifoToGet(outAudioFifo);
punk@11	604 endinterface
punk@11	605
punk@11	606
rlm@8	607 endmodule
rlm@8	608

Mercurial > pygar

annotate modules/bluespec/Pygar/core/Processor.bsv @ 11:50af57801d6e pygar svn.12