annotate modules/bluespec/Pygar/core/MemArb.bsv @ 11:50af57801d6e pygar svn.12

[svn r12] working on getting audio pipe processor working
author punk
date Sun, 25 Apr 2010 08:31:47 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 // The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@8 23 import Connectable::*;
rlm@8 24 import GetPut::*;
rlm@8 25 import ClientServer::*;
rlm@8 26 import FIFOF::*;
rlm@8 27 import FIFO::*;
rlm@8 28
rlm@8 29 import BFIFO::*;
rlm@8 30 import MemTypes::*;
rlm@8 31 import Trace::*;
rlm@8 32
rlm@8 33 interface MemArb;
rlm@8 34
rlm@8 35 interface Server#(MainMemReq,MainMemResp) cache0_server;
rlm@8 36 interface Server#(MainMemReq,MainMemResp) cache1_server;
rlm@8 37 interface Client#(MainMemReq,MainMemResp) mmem_client;
rlm@8 38
rlm@8 39 endinterface
rlm@8 40
rlm@8 41 typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits);
rlm@8 42
rlm@8 43 (* synthesize *)
rlm@8 44 module mkMemArb( MemArb );
rlm@8 45
rlm@8 46 //-----------------------------------------------------------
rlm@8 47 // State
rlm@8 48
rlm@8 49 FIFOF#(MainMemReq) req0Q <- mkFIFOF1();
rlm@8 50 FIFO#(MainMemResp) resp0Q <- mkFIFO1();
rlm@8 51
rlm@8 52 FIFOF#(MainMemReq) req1Q <- mkFIFOF1();
rlm@8 53 FIFO#(MainMemResp) resp1Q <- mkFIFO1();
rlm@8 54
rlm@8 55 FIFO#(MainMemReq) mreqQ <- mkFIFO1();
rlm@8 56 FIFO#(MainMemResp) mrespQ <- mkFIFO1();
rlm@8 57
rlm@8 58 Reg#(ReqPtr) nextReq <- mkReg(REQ0);
rlm@8 59
rlm@8 60 //-----------------------------------------------------------
rlm@8 61 // Some wires
rlm@8 62
rlm@8 63 let req0avail = req0Q.notEmpty();
rlm@8 64 let req1avail = req1Q.notEmpty();
rlm@8 65
rlm@8 66 //-----------------------------------------------------------
rlm@8 67 // Rules
rlm@8 68
rlm@8 69 rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) );
rlm@8 70 traceTiny("mkMemArb", "memArb req0",req0Q.first());
rlm@8 71
rlm@8 72 // Rewrite tag field if this is a load ...
rlm@8 73 MainMemReq mreq
rlm@8 74 = case ( req0Q.first() ) matches
rlm@8 75 tagged LoadReq .ld : return LoadReq { tag:0, addr:ld.addr };
rlm@8 76 tagged StoreReq .st : return req0Q.first();
rlm@8 77 endcase;
rlm@8 78
rlm@8 79 // Send out the request
rlm@8 80 mreqQ.enq(mreq);
rlm@8 81 nextReq <= REQ1;
rlm@8 82 req0Q.deq();
rlm@8 83
rlm@8 84 endrule
rlm@8 85
rlm@8 86 rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) );
rlm@8 87 traceTiny("mkMemArb", "memArb req1",req1Q.first);
rlm@8 88
rlm@8 89 // Rewrite tag field if this is a load ...
rlm@8 90 MainMemReq mreq
rlm@8 91 = case ( req1Q.first() ) matches
rlm@8 92 tagged LoadReq .ld : return LoadReq { tag:1, addr:ld.addr };
rlm@8 93 tagged StoreReq .st : return req1Q.first();
rlm@8 94 endcase;
rlm@8 95
rlm@8 96 // Send out the request
rlm@8 97 mreqQ.enq(mreq);
rlm@8 98 nextReq <= REQ0;
rlm@8 99 req1Q.deq();
rlm@8 100
rlm@8 101 endrule
rlm@8 102
rlm@8 103 rule returnResp;
rlm@8 104 traceTiny("mkMemArb", "resp",mrespQ.first());
rlm@8 105
rlm@8 106 // Use tag to figure out where to send response
rlm@8 107 mrespQ.deq();
rlm@8 108 let tag
rlm@8 109 = case ( mrespQ.first() ) matches
rlm@8 110 tagged LoadResp .ld : return ld.tag;
rlm@8 111 tagged StoreResp .st : return st.tag;
rlm@8 112 endcase;
rlm@8 113
rlm@8 114 if ( tag == 0 )
rlm@8 115 resp0Q.enq(mrespQ.first());
rlm@8 116 else
rlm@8 117 resp1Q.enq(mrespQ.first());
rlm@8 118
rlm@8 119 endrule
rlm@8 120
rlm@8 121 //-----------------------------------------------------------
rlm@8 122 // Methods
rlm@8 123
rlm@8 124 interface Server cache0_server;
rlm@8 125 interface Put request = toPut(req0Q);
rlm@8 126 interface Get response = toGet(resp0Q);
rlm@8 127 endinterface
rlm@8 128
rlm@8 129 interface Server cache1_server;
rlm@8 130 interface Put request = toPut(req1Q);
rlm@8 131 interface Get response = toGet(resp1Q);
rlm@8 132 endinterface
rlm@8 133
rlm@8 134 interface Client mmem_client;
rlm@8 135 interface Get request = toGet(mreqQ);
rlm@8 136 interface Put response = toPut(mrespQ);
rlm@8 137 endinterface
rlm@8 138
rlm@8 139 endmodule
rlm@8 140
rlm@8 141