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annotate modules/bluespec/Pygar/core/audioCore.bsv @ 56:4449e17a2237 pygar svn.57

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[svn r57] added useless stuff that should work but doesn't.
author rlm
date Sun, 09 May 2010 23:12:15 -0400
parents 9fe5ed4af92d
children cf8bb3038cbd
rev   line source
punk@13 1 // The MIT License
punk@13 2
punk@13 3 // Copyright (c) 2009 Massachusetts Institute of Technology
punk@13 4
punk@13 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@13 6 // of this software and associated documentation files (the "Software"), to deal
punk@13 7 // in the Software without restriction, including without limitation the rights
punk@13 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@13 9 // copies of the Software, and to permit persons to whom the Software is
punk@13 10 // furnished to do so, subject to the following conditions:
punk@13 11
punk@13 12 // The above copyright notice and this permission notice shall be included in
punk@13 13 // all copies or substantial portions of the Software.
punk@13 14
punk@13 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@13 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@13 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@13 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@13 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@13 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@13 21 // THE SOFTWARE.
punk@13 22
punk@13 23 import Connectable::*;
punk@13 24 import GetPut::*;
punk@13 25 import ClientServer::*;
punk@13 26 import Processor::*;
punk@13 27 import MemArb::*;
punk@13 28 import MemTypes::*;
punk@48 29 import FIFO::*;
punk@13 30
punk@13 31 //AWB includes
punk@13 32 `include "asim/provides/low_level_platform_interface.bsh"
punk@13 33 `include "asim/provides/soft_connections.bsh"
punk@13 34 `include "asim/provides/common_services.bsh"
punk@13 35
punk@13 36 // Local includes
punk@13 37 `include "asim/provides/processor_library.bsh"
punk@13 38 `include "asim/provides/mem_arb.bsh"
punk@13 39 `include "asim/provides/instruction_cache.bsh"
punk@13 40 `include "asim/provides/data_cache.bsh"
punk@13 41 `include "asim/provides/processor.bsh"
punk@15 42 `include "asim/provides/audio_pipe_types.bsh"
punk@15 43
punk@48 44 // Scratchpad includes
punk@48 45 `include "asim/provides/scratchpad_memory.bsh"
punk@48 46 `include "asim/provides/mem_services.bsh"
punk@48 47 `include "asim/dict/VDEV_SCRATCH.bsh"
punk@48 48
punk@21 49 interface Core;
punk@13 50
punk@15 51 interface Get#(AudioProcessorUnit) sampleOutput;
punk@36 52 interface Put#(AudioProcessorUnit) sampleInput;
punk@36 53
punk@36 54 // interface CPUToHost tohost;
punk@36 55
punk@13 56 endinterface
punk@13 57
punk@51 58 module [CONNECTED_MODULE] mkCore#(Integer prog) ( Core );
punk@48 59
punk@13 60
punk@13 61 // Instantiate the modules
punk@13 62
punk@13 63 Proc proc <- mkProc();
punk@13 64 ICache#(InstReq,InstResp) icache <- mkInstCache();
punk@13 65 DCache#(DataReq,DataResp) dcache <- mkDataCache();
punk@13 66 MemArb marb <- mkMemArb();
punk@51 67 MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(prog, SCRATCHPAD_CACHED); //Services Memory items
punk@13 68
punk@48 69 // Make this big enough so that several outstanding requests may be supported
punk@48 70 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
punk@48 71
punk@13 72 // Internal connections
punk@13 73
punk@13 74 mkConnection( proc.statsEn_get, icache.statsEn_put );
punk@13 75 mkConnection( proc.statsEn_get, dcache.statsEn_put );
punk@26 76 mkConnection( proc.imem_client, icache.proc_server );
punk@26 77 mkConnection( proc.dmem_client, dcache.proc_server );
punk@13 78 mkConnection( icache.mmem_client, marb.cache0_server );
punk@13 79 mkConnection( dcache.mmem_client, marb.cache1_server );
punk@13 80
punk@48 81 // Memory Access
punk@48 82 rule sendMemReq;
punk@48 83 let coreReq <- marb.mmem_client.request.get;
punk@48 84 case (coreReq) matches
punk@48 85 tagged LoadReq .load: begin
punk@48 86 // $display("PIPE Load Addr Req %h", load.addr);
punk@48 87 //Allocate ROB space
punk@48 88 memory.readReq(truncate(load.addr>>2));
punk@48 89 tags.enq(load.tag);
punk@48 90 end
punk@48 91 tagged StoreReq .store: begin
punk@48 92 // $display("PIPE Write Addr Req %h", store.addr);
punk@48 93 memory.write(truncate(store.addr>>2),store.data);
punk@48 94 end
punk@48 95 endcase
punk@48 96 endrule
punk@48 97
punk@48 98 rule receiveMemResp;
punk@48 99 let memResp <- memory.readRsp();
punk@48 100 tags.deq;
punk@48 101 marb.mmem_client.response.put(tagged LoadResp {data:memResp,
punk@48 102 tag: tags.first});
punk@48 103 // $display("PIPE Receive MemReq %x", memResp);
punk@48 104 endrule
punk@48 105
punk@13 106 // Methods
punk@48 107
punk@15 108 interface sampleOutput = proc.sampleOutput;
punk@36 109 interface sampleInput = proc.sampleInput;
punk@36 110
punk@36 111 // interface CPUToHost tohost = proc.tohost;
punk@13 112
punk@13 113 endmodule