annotate modules/bluespec/Pygar/lab4/BranchPred.bsv @ 41:16ba43f0a7c3
pygar svn.42
[svn r42] got channels working
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rlm |
| date |
Tue, 04 May 2010 22:32:52 -0400 |
| parents |
74716e9a81cc |
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1 import RegFile::*;
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2 import ProcTypes::*;
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3 import FIFO::*;
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4
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5 typedef Maybe#(Addr) BrPred;
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6 typedef Bit#(4) BPindx;
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7
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8 typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq);
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9
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10 typedef union tagged
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11 {
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12 BrPair Valid;
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13 void Invalid;
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14 } CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values.
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15
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16 interface BranchPred;
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17 method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition
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18 method Action upd(Addr pres, Addr next);
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19 endinterface
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20
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21 module mkBranchPred(BranchPred);
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22
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23 //state variables
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24 RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx)
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25
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26 method Action upd(Addr pres, Addr next);
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27 BrPair brp;
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28 brp = BrPair {brpc:pres, nextpc:next};
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29 bcache.upd(pres[5:2], tagged Valid brp);
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30 endmethod
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31
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32 method BrPred get(Addr prespc);
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33 BPindx rd = prespc[5:2];
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34 let cbp = bcache.sub(rd);
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35 if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches
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36 return tagged Valid bp.nextpc;
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37 else return Invalid;
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38 endmethod
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39
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40 endmodule
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41
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