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1 import FIFO::*;
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2 import FIFOF::*;
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3 import List::*;
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4 import Assert::*;
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5
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6 module mkBFIFO1( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) );
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7
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8 RWire#(item_t) inputWire <- mkRWire();
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9 PulseWire deqEnabled <- mkPulseWire();
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10 PulseWire clearEnabled <- mkPulseWire();
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11
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12 Reg#(item_t) register <- mkRegU();
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13 Reg#(Bool) valid <- mkReg(False);
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14
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15 // If there is an input item on the inputWire wire and dequeue did not
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16 // execute this cycle then we need to store the item in the register
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17
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18 (*fire_when_enabled*)
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19 rule update ( True );
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20 case (inputWire.wget()) matches
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21 tagged Invalid:
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22 if (deqEnabled || clearEnabled)
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23 valid <= False;
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24 tagged Valid .x:
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25 begin
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26 register <= x;
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27 valid <= !(deqEnabled || clearEnabled);
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28 end
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29 endcase
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30 endrule
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31
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32 // On enqueue we write the input item to the inputWire wire
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33
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34 method Action enq( item_t item ) if ( !valid );
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35 inputWire.wset(item);
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36 endmethod
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37
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38 // On dequeue we always invalidate the storage register regardless
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39 // of whether or not the item was actually bypassed or not. We also
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40 // set a combinational signal so that we know not to move the item
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41 // into the register this cycle.
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42
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43 method Action deq() if ( valid || isValid(inputWire.wget()) );
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44 deqEnabled.send();
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45 endmethod
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46
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47 // We get the item either from the register (if register is valid) or
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48 // from the combinational bypasss (if the rwire is valid).
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49
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50 method item_t first() if ( valid || isValid(inputWire.wget()) );
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51 if ( valid )
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52 return register;
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53 else
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54 return unJust(inputWire.wget());
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55 endmethod
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56
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57 method Action clear();
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58 clearEnabled.send();
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59 endmethod
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60
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61 endmodule
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62
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63 module mkSizedBFIFO#(Integer n) ( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) );
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64
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65 RWire#(item_t) inputWire <- mkRWire();
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66 PulseWire deqEnabled <- mkPulseWire();
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67 PulseWire clearEnabled <- mkPulseWire();
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68
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69 List#(Reg#(item_t)) registers <- replicateM(n, mkRegU);
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70 List#(Reg#(Bool)) valids <- replicateM(n, mkReg(False));
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71
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72 function Nat getNextFree (List#(Reg#(Bool)) vs);
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73
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74 Nat res = fromInteger(n - 1);
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75
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76 for (Integer x = n - 1; x > -1; x = x - 1)
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77 res = !vs[x]._read() ? fromInteger(x) : res;
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78
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79 return res;
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80
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81 endfunction
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82
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83 function Bool notFull();
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84
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85 Bool full = True;
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86
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87 for (Integer x = 0; x < length(valids); x = x + 1)
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88 full = full && valids[x]._read();
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89
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90 return !full;
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91
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92 endfunction
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93 // If there is an input item on the inputWire wire and dequeue did not
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94 // execute this cycle then we need to store the item in the register
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95
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96 rule update ( True );
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97 Nat next = getNextFree(valids);
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98
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99 next = (deqEnabled) ? next - 1 : next;
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100
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101 (valids[next]) <= isValid(inputWire.wget());
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102 (registers[next]) <= validValue(inputWire.wget());
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103
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104 if (deqEnabled && !clearEnabled)
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105 begin
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106
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107 for (Nat x = 0; x < (next - 1); x = x + 1)
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108 begin
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109 (valids[x]) <= valids[x+1]._read();
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110 (registers[x]) <= registers[x+1]._read();
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111 end
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112
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113 end
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114 else if (clearEnabled)
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115 begin
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116
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117 for (Integer x = 0; x < n; x = x + 1)
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118 (valids[x]) <= False;
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119
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120 end
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121 endrule
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122
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123 // On enqueue we write the input item to the inputWire wire
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124
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125 method Action enq( item_t item ) if ( notFull );
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126 inputWire.wset(item);
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127 endmethod
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128
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129 // On dequeue we always invalidate the storage register regardless
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130 // of whether or not the item was actually bypassed or not. We also
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131 // set a combinational signal so that we know not to move the item
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132 // into the register this cycle.
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133
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134 method Action deq() if ( valids[0]._read() || isValid(inputWire.wget()) );
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135 deqEnabled.send();
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136 endmethod
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137
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138 // We get the item either from the register (if register is valid) or
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139 // from the combinational bypasss (if the rwire is valid).
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140
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141 method item_t first() if ( valids[0]._read() || isValid(inputWire.wget()) );
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142 if ( valids[0]._read() )
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143 return registers[0]._read();
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144 else
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145 return unJust(inputWire.wget());
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146 endmethod
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147
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148
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149 method Action clear();
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150 clearEnabled.send();
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151 endmethod
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152
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153 endmodule
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154
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155
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156 module mkBFIFOF1( FIFOF#(item_t) ) provisos ( Bits#(item_t,item_sz) );
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157
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158 RWire#(item_t) inputWire <- mkRWire();
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159 RWire#(Bool) deqEnabled <- mkRWire();
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160
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161 Reg#(Maybe#(item_t)) register <- mkReg(Invalid);
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162
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163 // If there is an input item on the inputWire wire and dequeue did not
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164 // execute this cycle then we need to store the item in the register
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165
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166 rule noDeq ( isValid(inputWire.wget()) && !isValid(deqEnabled.wget()) );
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167 register <= inputWire.wget();
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168 endrule
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169
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170 // On enqueue we write the input item to the inputWire wire
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171
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172 method Action enq( item_t item ) if ( !isValid(register) );
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173 inputWire.wset(item);
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174 endmethod
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175
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176 // On dequeue we always invalidate the storage register regardless
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177 // of whether or not the item was actually bypassed or not. We also
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178 // set a combinational signal so that we know not to move the item
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179 // into the register this cycle.
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180
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181 method Action deq() if ( isValid(register) || isValid(inputWire.wget()) );
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182 register <= Invalid;
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183 deqEnabled.wset(True);
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184 endmethod
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185
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186 // We get the item either from the register (if register is valid) or
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187 // from the combinational bypasss (if the rwire is valid).
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188
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189 method item_t first() if ( isValid(register) || isValid(inputWire.wget()) );
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190 if ( isValid(register) )
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191 return unJust(register);
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192 else
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193 return unJust(inputWire.wget());
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194 endmethod
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195
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196 // FIFOF adds the following two methods
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197
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198 method Bool notFull();
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199 return !isValid(register);
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200 endmethod
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201
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202 method Bool notEmpty();
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203 return (isValid(register) || isValid(inputWire.wget()));
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204 endmethod
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205
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206 // Not sure about the clear method ...
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207
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208 method Action clear();
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209 dynamicAssert( False, "BFIFO.clear() not implemented yet!" );
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210 endmethod
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211
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212 endmodule
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213
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214 (* synthesize *)
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215 module mkBFIFO_16 (FIFO#(Bit#(16)));
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216
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217 let f <- mkBFIFO1();
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218
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219 return f;
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220
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221 endmodule
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222
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