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1 // The MIT License
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2
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3 // Copyright (c) 2009 Massachusetts Institute of Technology
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4
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5 // Permission is hereby granted, free of charge, to any person obtaining a copy
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6 // of this software and associated documentation files (the "Software"), to deal
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7 // in the Software without restriction, including without limitation the rights
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8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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9 // copies of the Software, and to permit persons to whom the Software is
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10 // furnished to do so, subject to the following conditions:
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11
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12 // The above copyright notice and this permission notice shall be included in
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13 // all copies or substantial portions of the Software.
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14
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15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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21 // THE SOFTWARE.
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22
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23 import Connectable::*;
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24 import GetPut::*;
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25 import ClientServer::*;
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26
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27 import DataCacheBlocking::*;
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28 import InstCacheBlocking::*;
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29 import Processor::*;
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30 import MemArb::*;
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31 import MemTypes::*;
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32
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33 `include "asim/provides/data_cache.bsh"
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34 `include "asim/provides/instruction_cache.bsh"
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35 `include "asim/provides/processor_library.bsh"
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36
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37 //interface CoreStats;
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38 // interface DCacheStats dcache;
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39 //interface ICacheStats icache;
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40 //interface ProcStats proc;
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41 //endinterface
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42
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43 interface Core;
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44
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45 // Interface from core to main memory
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46 interface Client#(MainMemReq,MainMemResp) mmem_client;
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47
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48 // Statistics
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49 // interface CoreStats stats;
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50
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51 // CPU to Host
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52 interface CPUToHost tohost;
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53
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54 // Interface to Audio Pipeline
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55 interface Audio audio;
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56
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57 endinterface
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58
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59 (* synthesize *)
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60 module mkCore(Core);
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61
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62 // Instantiate the modules
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63 Proc proc <- mkProc();
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64 ICache#(InstReq,InstResp) icache <- mkInstCache();
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65 DCache#(DataReq,DataResp) dcache <- mkDataCache();
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66 MemArb marb <- mkMemArb();
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67
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68 // Internal connections
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69 mkConnection( proc.statsEn_get, icache.statsEn_put );
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70 mkConnection( proc.statsEn_get, dcache.statsEn_put );
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71 mkConnection( proc.imem_client, icache.proc_server );
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72 mkConnection( proc.dmem_client, dcache.proc_server );
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73 mkConnection( icache.mmem_client, marb.cache0_server );
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74 mkConnection( dcache.mmem_client, marb.cache1_server );
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75
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76 // Methods
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77 interface mmem_client = marb.mmem_client;
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78
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79 // interface CoreStats stats;
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80 // interface dcache = dcache.stats;
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81 // interface icache = icache.stats;
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82 // interface proc = proc.stats;
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83 // endinterface
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84
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85 interface CPUToHost tohost = proc.tohost;
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86
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87 interface Audio audio = proc.audio;
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88
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89 endmodule
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90
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