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2 import Trace::*;
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3
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4 //----------------------------------------------------------------------
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5 // Other typedefs
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6 //----------------------------------------------------------------------
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7
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8 typedef Bit#(32) Addr;
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9
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10 //----------------------------------------------------------------------
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11 // Basic instruction type
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12 //----------------------------------------------------------------------
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13
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14 typedef Bit#(5) Rindx;
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15 typedef Bit#(16) Simm;
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16 typedef Bit#(16) Zimm;
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17 typedef Bit#(5) Shamt;
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18 typedef Bit#(26) Target;
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19 typedef Bit#(5) CP0indx;
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20
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21 typedef union tagged
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22 {
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23
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24 struct { Rindx rbase; Rindx rdst; Simm offset; } LW;
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25 struct { Rindx rbase; Rindx rsrc; Simm offset; } SW;
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26
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27 struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU;
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28 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI;
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29 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU;
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30 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI;
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31 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI;
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32 struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI;
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33 struct { Rindx rdst; Zimm imm; } LUI;
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34
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35 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL;
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36 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL;
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37 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA;
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38 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV;
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39 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV;
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40 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV;
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41 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU;
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42 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU;
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43 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND;
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44 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR;
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45 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR;
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46 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR;
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47 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT;
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48 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU;
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49
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50 struct { Target target; } J;
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51 struct { Target target; } JAL;
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52 struct { Rindx rsrc; } JR;
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53 struct { Rindx rsrc; Rindx rdst; } JALR;
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54 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ;
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55 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE;
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56 struct { Rindx rsrc; Simm offset; } BLEZ;
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57 struct { Rindx rsrc; Simm offset; } BGTZ;
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58 struct { Rindx rsrc; Simm offset; } BLTZ;
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59 struct { Rindx rsrc; Simm offset; } BGEZ;
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60
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61 struct { Rindx rdst; CP0indx cop0src; } MFC0;
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62 struct { Rindx rsrc; CP0indx cop0dst; } MTC0;
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63
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64 void ILLEGAL;
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65
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66 }
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67 Instr deriving(Eq);
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68
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69 //----------------------------------------------------------------------
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70 // Pack and Unpack
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71 //----------------------------------------------------------------------
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72
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73 Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000;
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74 Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010;
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75 Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011;
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76 Bit#(6) fcSLLV = 6'b000100;
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77 Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110;
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78 Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111;
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79 Bit#(6) fcADDU = 6'b100001;
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80 Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011;
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81 Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100;
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82 Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101;
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83 Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110;
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84 Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111;
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85 Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010;
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86 Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011;
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87
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88 Bit#(6) opJ = 6'b000010;
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89 Bit#(6) opJAL = 6'b000011;
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90 Bit#(6) fcJR = 6'b001000;
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91 Bit#(6) fcJALR = 6'b001001;
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92 Bit#(6) opBEQ = 6'b000100;
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93 Bit#(6) opBNE = 6'b000101;
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94 Bit#(6) opBLEZ = 6'b000110;
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95 Bit#(6) opBGTZ = 6'b000111;
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96 Bit#(5) rtBLTZ = 5'b00000;
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97 Bit#(5) rtBGEZ = 5'b00001;
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98
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99 Bit#(5) rsMFC0 = 5'b00000;
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100 Bit#(5) rsMTC0 = 5'b00100;
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101
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102 instance Bits#(Instr,32);
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103
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104 // Pack Function
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105
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106 function Bit#(32) pack( Instr instr );
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107
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108 case ( instr ) matches
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109
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110 tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset };
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111 tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset };
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112
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113 tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm };
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114 tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm };
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115 tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm };
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116 tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm };
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117 tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm };
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118 tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm };
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119 tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm };
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120
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121 tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL };
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122 tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL };
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123 tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA };
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124
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125 tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV };
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126 tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV };
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127 tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV };
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128
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129 tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU };
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130 tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU };
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131 tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND };
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132 tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR };
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133 tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR };
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134 tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR };
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135 tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT };
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136 tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU };
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137
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138 tagged J .it : return { opJ, it.target };
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139 tagged JAL .it : return { opJAL, it.target };
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140 tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR };
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141 tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR };
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142 tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset };
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143 tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset };
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144 tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset };
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145 tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset };
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146 tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset };
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147 tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset };
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148
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149 tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 };
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150 tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 };
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151
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152 endcase
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153
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154 endfunction
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155
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156 // Unpack Function
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157
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158 function Instr unpack( Bit#(32) instrBits );
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159
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160 let opcode = instrBits[ 31 : 26 ];
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161 let rs = instrBits[ 25 : 21 ];
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162 let rt = instrBits[ 20 : 16 ];
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163 let rd = instrBits[ 15 : 11 ];
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164 let shamt = instrBits[ 10 : 6 ];
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165 let funct = instrBits[ 5 : 0 ];
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166 let imm = instrBits[ 15 : 0 ];
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167 let target = instrBits[ 25 : 0 ];
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168
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169 case ( opcode )
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170
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171 opLW : return LW { rbase:rs, rdst:rt, offset:imm };
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172 opSW : return SW { rbase:rs, rsrc:rt, offset:imm };
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173 opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm };
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174 opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm };
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175 opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm };
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176 opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm };
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177 opORI : return ORI { rsrc:rs, rdst:rt, imm:imm };
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178 opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm };
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179 opLUI : return LUI { rdst:rt, imm:imm };
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180 opJ : return J { target:target };
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181 opJAL : return JAL { target:target };
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182 opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm };
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183 opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm };
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184 opBLEZ : return BLEZ { rsrc:rs, offset:imm };
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185 opBGTZ : return BGTZ { rsrc:rs, offset:imm };
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186
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187 opFUNC :
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188 case ( funct )
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189 fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt };
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190 fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt };
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191 fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt };
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192 fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs };
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193 fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs };
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194 fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs };
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195 fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd };
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196 fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd };
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197 fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd };
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198 fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd };
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199 fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd };
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200 fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd };
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201 fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd };
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202 fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd };
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203 fcJR : return JR { rsrc:rs };
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204 fcJALR : return JALR { rsrc:rs, rdst:rd };
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205 default : return ILLEGAL;
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206 endcase
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207
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208 opRT :
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209 case ( rt )
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210 rtBLTZ : return BLTZ { rsrc:rs, offset:imm };
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211 rtBGEZ : return BGEZ { rsrc:rs, offset:imm };
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212 default : return ILLEGAL;
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213 endcase
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214
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215 opRS :
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216 case ( rs )
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217 rsMFC0 : return MFC0 { rdst:rt, cop0src:rd };
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218 rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd };
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219 default : return ILLEGAL;
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220 endcase
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221
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222 default : return ILLEGAL;
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223
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224 endcase
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225
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226 endfunction
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227
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228 endinstance
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229
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230 //----------------------------------------------------------------------
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rlm@8
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231 // Trace
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232 //----------------------------------------------------------------------
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233
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234 instance Traceable#(Instr);
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235
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236 function Action traceTiny( String loc, String ttag, Instr inst );
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237 case ( inst ) matches
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238
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239 tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag );
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240 tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag );
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241
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242 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag );
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243 tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag );
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244 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag );
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245 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag );
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246 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag );
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247 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag );
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rlm@8
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248 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag );
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rlm@8
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249
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rlm@8
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250 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag );
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rlm@8
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251 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag );
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rlm@8
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252 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag );
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rlm@8
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253 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag );
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rlm@8
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254 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag );
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rlm@8
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255 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag );
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rlm@8
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256
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rlm@8
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257 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag );
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rlm@8
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258 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag );
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rlm@8
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259 tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag );
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rlm@8
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260 tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag );
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rlm@8
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261 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag );
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rlm@8
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262 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag );
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rlm@8
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263 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag );
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rlm@8
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264 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag );
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rlm@8
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265
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rlm@8
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266 tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag );
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rlm@8
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267 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag );
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rlm@8
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268 tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag );
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rlm@8
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269 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag );
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rlm@8
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270 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag );
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rlm@8
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271 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag );
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rlm@8
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272 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag );
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rlm@8
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273 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag );
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rlm@8
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274 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag );
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rlm@8
|
275 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag );
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rlm@8
|
276
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rlm@8
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277 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag );
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|
rlm@8
|
278 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag );
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rlm@8
|
279
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rlm@8
|
280 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag );
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|
rlm@8
|
281
|
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rlm@8
|
282 endcase
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|
rlm@8
|
283 endfunction
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|
rlm@8
|
284
|
|
rlm@8
|
285 function Action traceFull( String loc, String ttag, Instr inst );
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rlm@8
|
286 case ( inst ) matches
|
|
rlm@8
|
287
|
|
rlm@8
|
288 tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase );
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|
rlm@8
|
289 tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase );
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|
rlm@8
|
290
|
|
rlm@8
|
291 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
292 tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
293 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
294 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
295 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
296 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
297 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm );
|
|
rlm@8
|
298
|
|
rlm@8
|
299 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
|
|
rlm@8
|
300 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
|
|
rlm@8
|
301 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
|
|
rlm@8
|
302 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
|
|
rlm@8
|
303 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
|
|
rlm@8
|
304 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
|
|
rlm@8
|
305
|
|
rlm@8
|
306 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
307 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
308 tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
309 tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
310 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
311 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
312 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
313 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
314
|
|
rlm@8
|
315 tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target );
|
|
rlm@8
|
316 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target );
|
|
rlm@8
|
317 tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc );
|
|
rlm@8
|
318 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc );
|
|
rlm@8
|
319 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
|
|
rlm@8
|
320 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
|
|
rlm@8
|
321 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
|
|
rlm@8
|
322 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
|
|
rlm@8
|
323 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
|
|
rlm@8
|
324 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
|
|
rlm@8
|
325
|
|
rlm@8
|
326 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src );
|
|
rlm@8
|
327 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst );
|
|
rlm@8
|
328
|
|
rlm@8
|
329 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag );
|
|
rlm@8
|
330
|
|
rlm@8
|
331 endcase
|
|
rlm@8
|
332 endfunction
|
|
rlm@8
|
333
|
|
rlm@8
|
334 endinstance
|
|
rlm@8
|
335
|
